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Volumn 89, Issue 1, 2007, Pages 12-19

Design of a multi-level/analog ferroelectric memory device

Author keywords

Analog; Memory; Multi level; Transistor

Indexed keywords


EID: 70450238147     PISSN: 10584587     EISSN: 16078489     Source Type: Journal    
DOI: 10.1080/10584580601077435     Document Type: Conference Paper
Times cited : (7)

References (6)
  • 1
    • 7044263280 scopus 로고    scopus 로고
    • A nanoscale scalable memory architecture for molecular electronics
    • Y. Choi and Y. Kim, A nanoscale scalable memory architecture for molecular electronics. Nanotechnology, 15, S639-S644 PII (2004).
    • (2004) Nanotechnology , vol.15 , Issue.PII , pp. 639-644
    • Choi, Y.1    Kim, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.