Understanding the design trade-offs among current multicore systems for numerical computations

IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

Volumn , Issue , 2009, Pages

  Kang, Seunghwa ^a   Bader, David A ^a   Vuduc, Richard ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATOR TECHNOLOGY; BARCELONA; CELL BROADBAND ENGINE; COMPUTATIONAL STATISTICS; COMPUTING SYSTEM; DESIGN TRADEOFF; FUNDAMENTAL DESIGN; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; NUMERICAL COMPUTATIONS; SOFTWARE IMPLEMENTATION; TOSHIBA;

ARCHITECTURAL DESIGN; COMPUTER SOFTWARE; DISTRIBUTED PARAMETER NETWORKS; SOFTWARE ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 70449975572     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2009.5161055     Document Type: Conference Paper

References (31)

1. AMD CodeAnalyst, 2009. http://developer.amd.com/cpu/CodeAnalyst.
2. PAPI, 2009. http://icl.cs.utk.edu/papi.
3. The R project for statistical computing, 2009. http:// www.r-project.org/.
4. AMD Corporation. Software Optimization Guide for AMD Family 10h Processors, 3.06 edition, Apr. 2008.
5. O. Bockenbach, M. Knaup, and M. Kachelriess. Implementation of a cone-beam backprojection algorithm on the Cell Broadband Engine processor. In Proc. SPIE Medical Imaging, San Diego, CA, Feb. 2007.
6. S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron. A performance study of general-purpose applications on graphics processors using CUDA. Journal of Parallel and Distributed Computing, 68(10):1370-1380, 2008.
7. S. Che, J. Li, J.W. Sheaffer, K. Skadron, and J. Lach. Accelerating compute-intensive applications with GPUs and FPGAs. In Proc. 6th IEEE Symp. on Application Specific Processors (SASP), Anaheim, CA, Jun. 2008.
8. T. Chen, R. Raghavan, J. Dale, and E. Iwata. Cell Broadband Engine Architecture and its first implementation-a performance view. IBM Journal of Research and Developments, 51(5):559-572, Sep. 2007.
9. P. Gepner, D. L. Fraser, and M. F. Kowalik. Second generation quad-core Intel Xeon processors bring 45 nm technology and a new level of performance to HPC applications. Lecture Notes in Computer Science, 5101:417-426, 2008.
10. Intel Corporation. Intel 64 and IA-32 Architectures Optimization Reference Manual, Nov. 2007.
11. E. Ipek, O. Mutlu, J. F. Martinez, and R. Caruana. Selfoptimizing memory controllers: A reinforcement learning approach. ACM SIGARCH Computer Architecture News, 36(3):39-50, Jun. 2008.
12. D. Jimenez-Gonzalez, X. Martorell, and A. Ramirez. Performance analysis of Cell Broadband Engine for high memory bandwidth applications. In Proc. 7th IEEE Int'l Symp. on Performance Analysis of Systems and Software (ISPASS), San Jose, CA, Apr. 2007.
13. M. G. Kendall. A new measure of rank correlation. Biometrika Trust, 30(1):81-93, Jun. 1938.
14. E. Lindholm, J. Nickolls, S. Oberman, and J. Montrym. NVIDIA Tesla: A unified graphics and computing architecture. IEEE Micro, 28(2):39-55, Mar. 2008.
15. S. A. McKee, W. A. Wulf, J. H. Aylor, R. H. Klenke, M. H. Salinas, S. I. Hong, and D. A. B. Weikle. Dynamic access ordering for streamed computations. IEEE Transactions on Computers, 49(11):1255-1271, Nov. 2000.
16. J. S. Meredith, S. R. Alam, and J. S. Vetter. Analysis of a computational biology simulation technique on emerging processing architectures. In Proc. 6th IEEE Int'l Workshop on High Performance Computational Biology (HICOMB), Long Beach, CA, 2007.
17. O. Mutlu and T. Moscibroda. Enhancing the performance and fairness of shared DRAM systems with parallelismaware batch scheduling. In Proc. 35th Ann. Int'l Symp. on Computer Architecture (ISCA), Beijing, China, Jun. 2008.
18. C. Natarajan, B. Christenson, and F. Briggs. A study of performance impact of memory controller features in multiprocessor server environment. In Proc. 3rd Workshop on Memory Performance Issues (WMPI), Munich, Germany, Jun. 2004.
19. J. Nickolls, I. Buck, M. Garland, and K. Skadron. Scalable parallel programming with CUDA. ACM Queue, 6(2):40- 53, Mar. 2008.
20. NVIDIA Corporation. NVIDIA CUDA Compute Unified Device Architecture Programming Guide, 2.0 edition, Jun. 2008.
21. J. D. Owens, D. Luebke, N. Govindaraju, M. Harris, J. Kruger, A. E. Lefohn, and T. J. Purcell. A survey of general-purpose computation on graphics hardware. Computer Graphics Forum, 26(1):80-113, Mar. 2007.
22. L. A. Polka, H. Kalyanam, G. Hu, and S. Krishnamoorthy. Package technology to address the memory bandwidth challenge for tera-scale computing. Intel Technology Journal, 11(3), 2007.
23. N. Rafique, W. T. Lim, and M. Thottethodi. Effective management of DRAM bandwidth in multicore processors. In Proc. 16th Int'l Conf. on Parallel Architectures and Compilation Techniques (PACT), Brasov, Romania, Sep. 2007.
24. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory access scheduling. In Proc. 27th Ann. Int'l Symp. on Computer Architecture (ISCA), Vancouver, Canada, Jun. 2000.
25. S. Ryoo, C. I. Rodrigues, S. S. Baghsorkhi, S. S. Stone, D. B. Kirk, and W. W. Hwu. Optimization principles and application performance evaluation of a multithreaded GPU using CUDA. In Proc. 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Salt Lake City, UT, Feb. 2008.
26. S. Ryoo, C. I. Rodrigues, S. S. Stone, J. A. Stratton, S. Ueng, S. S. Baghsorkhi, and W. W. Hwu. Program optimization carving for GPU computing. Journal of Parallel and Distributed Computing, 68(10):1389-1401, 2008.
27. T. Saidani, S. Piskorski, L. Lacassagne, and S. Bouaziz. Parallelization schemes for memory optimization on the Cell processor: a case study of image processing algorithm. In Proc.Workshop on memory performance (MEDEA), Brasov, Romania, Sep. 2007.
28. O. Schenk, M. Christen, and H. Burkhart. Algorithmic performance studies on graphics processing units. Journal of Parallel and Distributed Computing, 68(10):1360-1369, 2008.
29. L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin, R. Espasa, E. Grochowski, T. Juan, and P. Hanrahan. Larrabee: a many-core x86 architecture for visual computing. ACM Transactions on Graphics, 27(3), Aug. 2008.
30. V. Volkov and J. W. Demmel. Benchmarking GPUs to tune dense linear algebra. In Proc. Int'l Conf. on High Performance Computing and Networking (SC), Austin, TX, 2008.
31. S. Williams, L. Oliker, R. Vuduc, J. Shalf, K. Yelick, and J. Demmel. Optimization of sparse matrix-vector multiplication on emerging multicore platforms. In Proc. Int'l Conf. on High Performance Computing and Networking (SC), 2007.