The electrical, mechanical properties of through-silicon-via insulation layer for 3D ICs

2009 International Conference on Electronic Packaging Technology and High Density Packaging, ICEPT-HDP 2009

Volumn , Issue , 2009, Pages 64-67

  Seo, Sang Woon ^a   Park, Jae Hyun ^b   Seo, Min K ^c   Kim, Gu Sung ^a  

^a Kangnam University   (South Korea)

^b EPWorks Co Ltd   (South Korea)

^c Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; DAMASCENE PROCESS; DEPOSITED LAYER; DEPOSITION CHARACTERISTICS; DEPOSITION PROCESS; ELECTRICAL CHARACTERISTIC; ELECTRICAL LEAKAGE; FAILURE RATE; INSULATING LAYERS; INSULATION LAYERS; INTER-DIFFUSION; PHYSICAL CHARACTERISTICS; SURFACE STEPS; TETRA-ETHYL-ORTHO-SILICATE; THIN LAYERS; THROUGH-SILICON-VIA; TIME DEPENDENT DIELECTRIC BREAKDOWN; VIA HOLE; VOLTAGE LEVELS;

DEPOSITION; DIELECTRIC MATERIALS; ELECTRIC PROPERTIES; ELECTRONICS PACKAGING; EXPERIMENTS; INSULATING MATERIALS; INSULATION; LEAKAGE CURRENTS; MECHANICAL PROPERTIES; PACKAGING; PLASMA DEPOSITION; REACTIVE ION ETCHING; SILICATES; SILICON OXIDES; SURFACE CHEMISTRY;

PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION;

EID: 70449971106     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICEPT.2009.5270794     Document Type: Conference Paper

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