Cooperative shared resource access control for low-power chip multiprocessors

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 177-182

  Takagi, Noriko ^a   Sasaki, Hiroshi ^b   Kondo, Masaaki ^c   Nakamura, Hiroshi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

Author keywords

Cache partitioning; Chip multiprocessors; DVFS; Low power; Resource conflict

Indexed keywords

CACHE PARTITIONING; CHIP MULTIPROCESSOR; DUAL-CORE; DYNAMIC VOLTAGE AND FREQUENCY SCALING; LOW POWER; MEMORY HIERARCHY; MULTIPLE PROCESSORS; PERFORMANCE CONSTRAINTS; POWER CONSUMPTION; POWER CONSUMPTION MODEL; RESOURCE CONFLICT; SHARED RESOURCES; SINGLE-CHIP MULTIPROCESSORS; TOTAL POWER CONSUMPTION;

ELECTRIC POWER UTILIZATION; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; POWER ELECTRONICS; SECURITY SYSTEMS; SYSTEMS ANALYSIS;

ACCESS CONTROL;

EID: 70449730915     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594278     Document Type: Conference Paper

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