Power reduction of chip multi-processors using shared resource control cooperating with DVFS

2007 IEEE International Conference on Computer Design, ICCD 2007

Volumn , Issue , 2007, Pages 615-622

  Watanabe, Ryo ^a   Kondo, Masaaki ^a   Nakamura, Hiroshi ^a   Nanya, Takashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CLOCKS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; REAL TIME SYSTEMS;

ANALYTICAL MODELLING; CHIP MULTI-PROCESSORS; CLOCK FREQUENCIES; COMPUTER DESIGNS; DUAL CORES; DYNAMIC VOLTAGE AND FREQUENCY SCALING; EVALUATION RESULTS; INTERNATIONAL CONFERENCES; PERFORMANCE IMPACTS; POWER CONSUMPTION; POWER REDUCTIONS; PROCESSING UNITS; REAL APPLICATIONS; REAL-TIME CONSTRAINTS; RESOURCE CONTROL; SHARED RESOURCES; SYNTHETIC BENCHMARK; TOTAL POWER CONSUMPTION;

ELECTRIC POWER UTILIZATION;

EID: 52949134455     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2007.4601961     Document Type: Conference Paper

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