EOS/ESD protection circuit design for deep submicron SOI technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1995, Pages 212-217

  Ramaswamy, Sridhar ^a   Raha, Prasun ^a   Rosenbaum, Elyse ^a   Kang, Sung Mo ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC DISCHARGES; ELECTRIC RESISTANCE; ELECTROSTATICS; FAILURE ANALYSIS; HEAT TRANSFER; MOS DEVICES; PROTECTION; SILICON ON INSULATOR TECHNOLOGY;

ELECTROSTATIC DISCHARGE; GATE OXIDES; PROTECTION CIRCUIT DESIGN; SILICON FILM THICKNESS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029537444     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/eosesd.1995.478287     Document Type: Conference Paper

References (13)