ESD evaluation of the emerging MuGFET technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2005, Pages

  Russ, Christian ^a   Gossner, Harald ^a   Schulz, Thomas ^a,c   Chaudhary, Nirmal ^a,c   Xiong, Weize ^b,c   Marshall, Andrew ^b   Duvvury, Charvaka ^b   Schruefer, Klaus ^a   Cleavelin, C Rinn ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b TEXAS INSTRUMENTS   (United States)

^c ATDF Advanced Technolgy Development Facility Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ESD PROTECTION; ESD STRESS; FINFET DEVICES; FULLY DEPLETED; GATED DIODES; IV CHARACTERISTICS; MULTIPLE GATES; PLANAR DEVICES; PLANAR STRUCTURE;

ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR);

MOS DEVICES;

EID: 70449726739     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. W. Xiong, G. Gebara, J. Zaman, M. Gostkowski, B. Nguyen, G. Smith, D. Lewis, C. R. Cleavelin, S. Yu, M. Pas, T.-J. King, J.P. Colinge, "Improvement of FinFET Electrical Characteristics by Hydrogen Annealing", IEEE Electron Device Letters, 2004, pp. 541-543.
2. S. Ramaswamy, P. Raha, E. Rosenbaum, S.-M. Kang, "EOS/ESD Protection Circuit Design for Deep Submicron SOI Technology", Proc. EOS/ESD 1995, pp. 212-217.
3. S. Voldman, F. Assaderaghi, J. Mandelman, L. Hsu, G. Shahidi, "Dynamic Threshold Body and Gate-Coupled SOI ESD Protection Networks", Proc. EOS/ESD 1997, pp. 210-220.
4. S. Voldman, D. Hui, L. Warriner, D. Young, J. Howard, F. Assaderaghi, G. Shahidi, "Electrostatic Discharge (ESD) Protection in Silicon-on-Insulator (SOI) CMOS Technology with Aluminum and Copper Interconnects in Advanced Microprocessor Semiconductor Chips", Proc. EOS/ESD 1999, pp. 105-115.
5. C. Duvvury et al., "ESD Design for Deep Submicron SOI Technology", Symp. VSLI Technology, 1996, pp. 194-195.
6. A. Salman, M. Pelella, S. Beebe, N. Subba, "ESD Protection for SOI Technology using an Under-The-Box (Substrate) Diode Structure", Proc. EOS/ESD 2004, pp. 248-254.