Exploring microprocessor architectures for gigascale integration

Proceedings - 20th Anniversary Conference on Advanced Research in VLSI, ARVLSI 1999

Volumn , Issue , 1999, Pages 242-255

  Codrescu, Lucian ^a   Deb Pant, Mondira ^a   Taha, Tarek ^a   Eble, John ^a   Wills, Scott ^a   Meindl, James ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT INTERCONNECTS; VLSI CIRCUITS;

GIGASCALE INTEGRATION; HIGHLY PARALLELS; LIMITED PARALLELISM; MICROPROCESSOR ARCHITECTURES; PARALLEL SYSTEM; PARALLEL WORKLOADS; UNIPROCESSORS; WIRE DELAYS;

PARALLEL PROCESSING SYSTEMS;

EID: 70449469059     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1999.756052     Document Type: Conference Paper

References (26)

1. P. Ahuja, D. Clark, A. Rogers, "Performance impact of incomplete bypassing in processor pipeline, " in Micro-28, pp. 36-45, December 1995
2. H. B. Bakoglu, "Circuits, Interconnection, and Packaging for VLSI, " Addison Wesley, '90.
3. D. Burger, T. A. Austin, "The SimpleScalar Tool Set, Version 2. 0", Technical Report #1342, University of Wisconsin-Madison Computer Science, June 1997.
4. M. Butler, T Yeh, Y. Patt, M. Alsup, H. Scales, M. Shebanow, "Single Instruction Stream Parallelism is Greater than Two, " ISCA-18, pp. 276-286, 1991.
5. CPU Info Center, at http://infopad. eecs. Berkeley. edu/CIC
6. J. C. Eble, V. K. De, D. S. Wills, J. D. Meindl, A Generic System Simulator (GENESYS) for ASIC Technology and Architecture Beyond 2001, in Proceedings of the Ninth Annual IEEE International ASIC Conference, pages 193-196, Rochester, NY, September 1996.
7. Matthew Farrens, Gary Tyson and Andrew R. Pleszkun, "A Study of Single-Chip Processor/Cache Organizations for Large Number of Transistors, " ISCA '94
8. Steve Fu and Michael Flynn, "Area and Performance Analysis of Processor Configurations with Scaling of Technology, " Technical Report:Stanford Univ, Mar '94.
9. Tetsuya Hara, Hideki Ando, Chikako Nakanishi and Masao Nakaya, "Performance Comparison of ILP Machines with Cycle Time Evaluation, " ISCA '96.
10. M. S. Lam and R. P. Wilson, "Limits of Control Flow on Parallelism, " ISCA-19, pp. 46-57, 1992
11. M. H. Lipasti, and J. P. Shen, "Exceeding the dataflow limit via value prediction, " in Micro-29, pp. 226-237, December 1996
12. S. A. Mahlke, R. E. Hank, J. E. McCormick, D. I. August, and W. W. Hwu, "A Comparison of Full and Partial Predicated Execution Support for ILP Processors, " in ISCA-22, pp. 138-149, June 1995
13. S. McFarling, "Combining Branch Predictors", Technical Report TN-36, Digital Western Research Laboratory, June 1993.
14. James Meindl, "Gigascale Integration: Is the Sky the Limit" IEEE Circuits and Devices, November 1996
15. "The National Technology Roadmap for Semiconductors, Technology Needs", SIA '97.
16. Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chung, "The Case for a Single-Chip Multiprocessor, "in ASPLOS-7, October 1996.
17. Jeffery Oplinger, David Heine, Shih-Wei Liao, Basem A. Nayfeh, Monica S. Lam, and Kunle Olukotun, "Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor, " Tech. Rep. CSL-TR-97-715, Computer Systems Laboratory, Stanford University, May 1997
18. Subbarao Palacharla, Norman P. Jouppi, and James E. Smith "Quanitfying the Complexity of Superscalar Processors, " ISCA '97.
19. Patterson, D. et al., "Scalable Processors in the Billion Transistor Era: IRAM", IEEE Computer Special Issue: Future Microprocessors-How to use a Billion Transistors, September 1997.
20. E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. E. Smith, et al, "Trace Processors", in Micro-30, pp. 68-74, December 1997
21. Gurindar S. Sohi, Scott E. Breach, and T. N. Vijaykumar, "Multiscalar processors, " in ISCA-22, pp. 414-425, June 1995
22. J. Gregory Steffan and Todd C. Mowry, "The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization, " in HPCA, February 1998
23. J.-Y. Tsai and P.-C. Yew, "The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation", in PACT, October 1996
24. Dean M. Tullsen, Susan J. Eggers, and Henry M. Levy, "Simultaneous multithreading: Maximizing on-chip parallelism, " in ISCA-22, pp. 392-403, June 1995
25. David. W. Wall "Limits of Instruction-Level Parallelism, " ASPLOS-4, pp. 176-188, 1991
26. Wulf, W. A., McKee, S. A. "Hitting the memory wall: implications of the obvious, " Computer Architecture News, March 1995, vol. 23, (no. 1):20-4.