A 188-size 2.1mm2 reconfigurable turbo decoder chip with parallel architecture for 3GPP LTE system

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 288-289

  Wong, Cheng Chi ^a   Lee, Yung Yu ^a   Chang, Hsie Chia ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

3GPP LTE; And QPP interleaver; Turbo decoder

Indexed keywords

3GPP LTE; AND QPP INTERLEAVER; BLOCK SIZES; MEMORY MODULES; NUMBER OF ITERATIONS; RE-CONFIGURABLE; SISO DECODER; TURBO DECODER; TURBO DECODERS;

PARALLEL ARCHITECTURES; VLSI CIRCUITS;

DECODING;

EID: 70449382446     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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