A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Sekikawa, M ^a   Kiyoyama, K ^a   Hasegawa, H ^a   Miura, K ^b   Fukushima, T ^a   Ikeda, S ^a   Tanaka, T ^a   Ohno, H ^a   Koyanagi, M ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS LOGIC; FULLY INTEGRATED; MAGNETIC ELEMENTS; MAGNETIC RESISTANCES; MR RATIOS; RE-CONFIGURABLE; READ-OUT OPERATIONS; RECONFIGURABLE LOGIC BLOCKS; SPIN PROCESSORS; SPIN-TRANSFER TORQUES;

ELECTRON DEVICES; POLARIZATION; RANDOM ACCESS STORAGE;

SPIN DYNAMICS;

EID: 78650761039     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796645     Document Type: Conference Paper

References (4)

1. M. Koyanagi et al., "Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections," IEEE Trans. Electron Devices, vol. 53, pp. 2799-2808, Nov. 2006.
2. M. Hosomi et al., "A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram," Proc. of IEEE Intl. Electron Devices Meeting, IEDM2005, pp. 459-462, Dec. 5-7, 2005.
3. C. Chappert et al., "The emergence of spin electronics in data storage," Nature materials, vol. 6, pp. 813-823, Nov. 2007.
4. T. Kawahara et al., "2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read," IEEE J. Solid-State Circuits, vol. 43, pp. 109-120, Jan. 2008.