A Reliable architecture for parallel implementations of the advanced encryption standard

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 25, Issue 4-5, 2009, Pages 269-278

  Di Natale, G ^a   Doulcier, M ^a   Flottes, M L ^a   Rouzeyre, B ^a  

^a LIRMM   (France)

Author keywords

AES; On line self test

Indexed keywords

ADVANCED ENCRYPTION STANDARD; AES; ARCHITECTURAL MODIFICATION; AREA OVERHEAD; FUNCTIONAL REDUNDANCY; HARDWARE IMPLEMENTATIONS; LOW COSTS; ON-LINE FAULT DETECTION; ON-LINE SELF-TEST; ON-LINE TESTS; PARALLEL IMPLEMENTATIONS; POWER ANALYSIS; SELF-TEST; SIDE CHANNEL ATTACK; SPATIAL REPLICATION;

FAULT DETECTION; HARDWARE; PARALLEL ARCHITECTURES;

CRYPTOGRAPHY;

EID: 70350525055     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/s10836-009-5106-6     Document Type: Article

References (10)

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