Rewiring using IRredundancy removal and addition

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 324-327

  Lin, Chun Chi ^a   Wang, Chun Yao ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

RE-STRUCTURING TECHNIQUES;

LOGIC DESIGN; TARGETS;

WIRE;

EID: 70350068758     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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7. L. A. Entrena, et al, "Combinational and Sequential Logic Optimization by Redundancy Addition and Removal," IEEE TCAD., vol. 14, pp. 909-916, July 1995.
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9. W. Kunz, et al, "Recursive Learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits", in Proc. ITC., pp. 816-825, 1992.
10. E. M. Sentovich, et al, "SIS: A System for Sequential Circuit Synthesis," Technical Report UCB/ERL M92/41, May 1992.