Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 63-68

  Chengmo, Yang ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVITY; CHIP SIZES; COMMUNICATION PATH; COMPUTING ENGINES; DEGREE OF FREEDOM; DYNAMIC VARIABILITY; EXECUTION ENVIRONMENTS; GRAPH REPRESENTATION MODEL; INTEGRATION DENSITY; PERFORMANCE DEGRADATION; PHYSICAL CORE; RELIABILITY PROBLEMS; RESOURCE VARIATIONS; RUNTIMES; SCHEDULE LENGTH; TASK ASSIGNMENT; WORST-CASE PERFORMANCE;

EID: 70350062101     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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