A monitor interconnect and support subsystem for multicore processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 761-766

  Madduri, Sailaja ^a   Vadlamani, Ramakrishna ^a   Burleson, Wayne ^a   Tessier, Russell ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT INTERCONNECTS; VOLTAGE SCALING;

ARCHITECTURAL APPROACH; ARCHITECTURAL INTERFACES; DEDICATED PROCESSORS; DYNAMIC VOLTAGE AND FREQUENCY SCALING; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; ON CHIP INTERCONNECT; SYSTEM LEVEL SIMULATOR;

DYNAMIC FREQUENCY SCALING;

EID: 70350051184     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090766     Document Type: Conference Paper

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