Power estimation methodology for VLIW digital signal processors

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn , Issue , 2008, Pages 1840-1844

  Ibrahim, Mostafa E A ^a,b   Rupp, Markus ^a   Fahmy, Hossam A H ^b  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^b CAIRO UNIVERSITY   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN PROCESS; ESTIMATION ERRORS; FUNCTIONAL LEVELS; HARDWARE ARCHITECTURE; LOW LEVEL; MODELING APPROACH; POWER CONSUMPTION; POWER ESTIMATIONS; SIGNAL AND IMAGE PROCESSING; SOFTWARE ALGORITHMS; VLIW PROCESSOR;

COMPUTER SOFTWARE; ELECTRIC POWER UTILIZATION; ESTIMATION; IMAGE PROCESSING; IMAGING SYSTEMS; SIGNAL PROCESSING; SOFTWARE ARCHITECTURE; VERY LONG INSTRUCTION WORD ARCHITECTURE;

DIGITAL SIGNAL PROCESSORS;

EID: 70349686909     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.2008.5074746     Document Type: Conference Paper

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