Challenges in stacked CSP packaging technology

2006 International Conference on Electronic Materials and Packaging, EMAP

Volumn , Issue , 2006, Pages

  Boon, Howe Oh ^a   Howe, Yin Loo ^a   Poh, Tat Oh ^a   Eng, Kwong Lee ^a  

^a Intel Technology Malaysia Sdn Bhd   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER NETWORKS; COMPUTER OPERATING PROCEDURES; ELECTRONICS INDUSTRY; PACKAGING MATERIALS; SILICON;

ELECTRONIC MATERIALS AND PACKAGING; INTERNATIONAL CONFERENCES; MEMORY CHIPS;

ELECTRONICS PACKAGING;

EID: 51449122954     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EMAP.2006.4430609     Document Type: Conference Paper

References (4)

1. Tiao Zhou', Mark Gerber' and Moody Dreiza2, "Stacked Die Package Design Guidelines," Texas Instruments', Amkor Technology2.
2. Bob Chylak and Ivy Wei Qin Kulicke & Soffa, "Packaging Challenges and Solutions for Multi-Stack Die Applications," SEMI Technology Symposium: IEMT Symposium, Chine 2003.
3. Lu-Vong T Phan & Amy Chen, "Dual Core Challenges in Design and Validation" Intel internal Document.
4. Martin Rausch, "Packaging Technology Challenges" Intel internal Document..