Post-dicing particle control for 3D stacked IC integration flows

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 1513-1516

  Bearda, Twan ^a   Travaly, Youssef ^a   Wostyn, Kurt ^a   Halder, Sandip ^a   Swinnen, Bart ^a   Mölders, Thomas ^b   Varghese, Ivin ^c   Cheng, Paul ^c  

^a IMEC   (Belgium)

^b Camtek Europe NV ^*  (Belgium)

^c Eco Snow Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; CLEANING PROCESS; DEFECT INSPECTION; HIGH YIELD; IN-PROCESS; LOW COSTS; PARTICLE CONTROL; PROCESS STEPS; VIABLE SOLUTIONS;

THREE DIMENSIONAL;

CLEANING;

EID: 70349663675     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074213     Document Type: Conference Paper

References (5)

1. B. Swinnen et al.: "3D integration by Cu-Cu thermocompression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias", International Electron Devices Meeting - IEDM. Technical Digest, San Francisco, CA, December 11-13, 2006.
2. A. Jourdain et al.: "Simultaneous Cu-Cu and compliant dielectric bonding for 3D stacking of ICs", Proceedings of the IEEE International Interconnect Technology Conference- IITC, Burlingame, CA, July 4-6, 2007 pp. 207-209.
3. J. Van Olmen et al.: "3D Stacked IC Demonstration using a Trough Silicon Via First Approach", to be published at International Electron Devices Meeting - IEDM. 2008.
4. T. Bearda et al.: "The Effect of Backside Particles on Substrate Topography", Japanese Journal of Applied Physics 44 (2005) pp. 7409-7413.
5. K. A. Reinhardt and W. Kern: "Handbook of Silicon Wafer Cleaning Technology", 2nd edition, William Andrew (Norwich NY) 2008.