Sensing design issues in deep submicron CMOS SRAMs

Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

Volumn , Issue , 2005, Pages 42-45

  Natarajan, Aiyappan ^a   Shankar, Vijay ^a   Maheshwari, Atul ^a   Burleson, Wayne ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DESIGN ISSUES; PROCESS VARIATION; SENSE-AMPLIFIERS;

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; SENSORS; STATIC RANDOM ACCESS STORAGE;

PRODUCT DESIGN;

EID: 26844435103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2005.67     Document Type: Conference Paper

References (6)

1. Berkeley Predictive Technology Model, http://www-eecs.device.berkely.edu/ ~ptm
2. T. Uteke et. al., "A 1.0ns access 770 MHz 36 Kb SRAM Macro", ISSCC Digest of Technical Papers, 1997, pp. 176-177
3. B. Giseke et. al., "A 600 MHz superscalar RISC Microprocessor with out of order execution", IEEE Journal of solid-state Circuits, 1991, pp. 542-548
4. T. Blalock and R. Jaeger, "A High Speed Clamped Bit-line Sense Amplifier," IEEE Journal of Solid State Circuits, April 1991, pp. 542-548.
5. M. Sinha et. al., "Low voltage sensing techniques and secondary design issues for sub 90nm caches," ESSCIRC, 2003, pp. 413-416
6. K. Agawa et. al., "A Bitline Leakage Compensation Schemet for Low-voltage SRAMS," IEEE Journal of solid-state Circuits, May 2001, pp. 726-734.