Impact of chip package interaction on Cu/ultra low-k interconnect delamination in flip chip package with large die

Proceedings of the 2009 IEEE International Interconnect Technology Conference, IITC 2009

Volumn , Issue , 2009, Pages 217-219

  Uchibori, Chihiro J ^a   Lee, Michael ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-PACKAGE INTERACTION; COOLING PROCESS; DIE SIZE; FLIP-CHIP PACKAGES; ON CHIPS; THEORETICAL STUDY; THERMAL ANALYSIS;

FLIP CHIP DEVICES; MECHANICAL PROPERTIES; THERMOANALYSIS;

DIES;

EID: 70349448670     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2009.5090392     Document Type: Conference Paper

References (9)

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3. G. Wang et al., "Packaging effects on reliability of Cu/low-k interconnects", IEEE Trans. Dev. and Mat. Reliability, vol. 2, pp. 119-128, Dec. 2003.
4. Lei L. Mercado et al., "Impact of Flip-Chip Packaging on Copper/Low-k Structures", IEEE Trans. Adv. Packaging, vol. 26, pp. 433-440, November 2003.
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6. Chihiro J. UCHIBORI et al., "Effects of Chip-Package Interaction on Mechanical Reliability of Cu Interconnects for 65nm Technology Node and Beyond", in Proc. Inter. Interconnect Tech. Conf. (IITC 2006), 196-198.
7. Chihiro J. UCHIBORI et al., "Investigation of Interconnect Design on Chip Package Interaction and Mechanical Reliability of Cu/low-k Multi-Layer Interconnects in Flip Chip Package", in Proc. Inter. Interconnect Tech. Conf. (IITC 2008), 150-152.
8. C. J. Zhai et al., "Investigation of Cu/low-k film delamination in flip chip packages", in Proc. 56th Electronic Components and Technol. Conf., 2006, pp. 709-717.
9. E. Suhir, "Interfacial Stresses in Bimetal Thermostats", J. Appl. Mech., 56, pp. 595-600, 1989.