A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 54-55

  Dickson, Timothy O ^a   Bulzacchelli, John F ^a   Friedman, Daniel J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECISION FEEDBACK EQUALIZERS; RAILS; TECHNOLOGY; VLSI CIRCUITS;

AREA SAVINGS; DECISION FEED BACK; FEEDBACK ARCHITECTURES; FREQUENCY-DEPENDENT; LOW POWERS; RAIL-TO-RAIL; SERIAL RECEIVERS; SOI CMOS;

ENERGY CONSERVATION;

EID: 51949086958     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585949     Document Type: Conference Paper

References (4)

1. A. Emami-Neyestanak et al., "A low-power receiver with switched-capacitor summation DFE," Dig. Symp. VLSI Circuits, pp. 192-193, June 2006.
2. A. Rylyakov, "An 11Gb/s 2.4mW half-rate sampling 2-tap DFE receiver in 65nm CMOS," Dig. Symp. VLSI Circuits, pp. 272-273, June 2007.
3. M. Park et al., "A 7Gb/s 9.3mW 2-Tap current integrating DFE receiver," ISSCC Dig Tech Papers, pp 230-231, Feb. 2007.
4. K.-L. Wong et al., "A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-tap DFE using soft decisions," Dig. Symp. VLSI Circuits, pp. 190-191, June 2006.