Low power architecture and design techniques for mobile handset LSI Medity™ M2

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 748-753

  Kunie, Shuichi ^a   Hiraga, Takefumi ^a   Tokue, Tatsuya ^a   Torii, Sunao ^b   Ohsawa, Taku ^b  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; INDUSTRIAL ENGINEERING; LSI CIRCUITS; TELEPHONE SETS;

APPLICATION PROCESSORS; BIAS CONTROL; CLOCK CONTROL; DESIGN AUTOMATION CONFERENCE; DESIGN TECHNIQUES; DIGITAL BASEBAND; HARDWARE MANAGEMENT; HIGH RESOLUTIONS; LOW-POWER ARCHITECTURE; MEASUREMENT RESULTS; MOBILE HANDSETS; MULTIMEDIA APPLICATIONS; ON CHIPS; POWER CONSUMPTION; SOUTH PACIFIC;

ARCHITECTURAL DESIGN;

EID: 49549113566     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4484051     Document Type: Conference Paper

References (3)

1. Nomura, M. et al., "Delay and Power Monitoring Schemes for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes, "IEEE J. of Solid-State Circuits, vol. 41, no.4, pp.805-814, Apr. 2006.
2. Torii, S. et al., "A 600MIPS120mW 70uA Leakage Triple-CPU Mobile Application Processor Chip," ISSCC Digest of Technical Papers, pp.136-137, Feb.2005.
3. Royannez, P. et al., "90nm Low Leakage SoC Design Techniques for Wireless Applications," ISSCC Digest of Technical Papers, pp.138-139, Feb.2005.