A 7Gb/s 9.3mW 2-Tap current-integrating DFE receiver

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 230-232

  Park, Matt ^a   Bulzacchelli, John ^b   Beakes, Michael ^b   Friedman, Daniel ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; BUFFER CIRCUITS; ELECTRIC CURRENTS; ENERGY DISSIPATION; SIGNAL RECEIVERS;

CLOCK BUFFERS; DFE RECEIVERS; RESETTABLE INTEGRATORS;

CMOS INTEGRATED CIRCUITS;

EID: 34548837459     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373378     Document Type: Conference Paper

References (2)

1. S. Bae, H. Chi, Y. Sohn, et al., "A 2 Gb/s 2-Tap DFE Receiver for Mult-Drop Single-Ended Signaling Systems with Reduced Noise," ISSCC Dig. Tech. Papers, pp. 244-245, Feb., 2004.
2. T. Beukema, M. Soma, K. Selander, et al., "A 6.4 GlVs CMOS SerDes Core with Feedforward and Decision-Feedback Equalization," IEEE J. Solid-State Circuits, pp. 2633-2645, Dec., 2005.