메뉴 건너뛰기




Volumn 3, Issue , 2004, Pages 1621-1624

High performance synchronous DRAMs controller in H.264 HDTV decoder

Author keywords

H.264; HDTV; Memory controller; SDRAMs

Indexed keywords

BANDWIDTH; CONTROL EQUIPMENT; DECODING; HIGH DEFINITION TELEVISION; IMAGE CODING; MEMBERSHIP FUNCTIONS; MOTION COMPENSATION; VLSI CIRCUITS;

EID: 21644476517     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (21)

References (8)
  • 2
    • 0035509949 scopus 로고    scopus 로고
    • High-performance and low-power memory-interface architecture for video processing application
    • Nov.
    • Hansoo Kim and In-Cheol Park, "High-Performance and Low-Power Memory-Interface Architecture for Video Processing Application", IEEE Trans. Circuits Syst. Video Tech.,. vol 11, pp1160-1170, Nov. 2001
    • (2001) IEEE Trans. Circuits Syst. Video Tech. , vol.11 , pp. 1160-1170
    • Kim, H.1    Park, I.-C.2
  • 3
    • 0029194177 scopus 로고
    • Architecture and memory requirements for stand-alone and hierarchical MPEG2 HDTV-decoders with synchronous DRAMs
    • May
    • Marco Winzker, Peter Pirsch, Jochen Reimers, "Architecture and Memory Requirements for stand-alone and hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs", ISCAS '95, IEEE Inter. Sym., pp609-612, May 1995
    • (1995) ISCAS '95, IEEE Inter. Sym. , pp. 609-612
    • Winzker, M.1    Pirsch, P.2    Reimers, J.3
  • 4
    • 0000906881 scopus 로고    scopus 로고
    • High performance and cost effective memory architecture for an HDTV decoder LSI
    • Mar.
    • Tetsuro Takizawa, Junju Tajime and Hidenobu Harasaki, "High Performance and Cost Effective Memory Architecture for an HDTV Decoder LSI", ICASSP '99. Proceedings, vol4, pp1981-1984, Mar. 1999
    • (1999) ICASSP '99. Proceedings , vol.4 , pp. 1981-1984
    • Takizawa, T.1    Tajime, J.2    Harasaki, H.3
  • 5
    • 0037481109 scopus 로고    scopus 로고
    • Efficient memory IP design for HDTV coding applications
    • June
    • Shih-Chang Hsia, "Efficient Memory IP Design for HDTV Coding Applications", IEEE Trans. Circuits Syst. Video Tech., vol 13, pp465-471, June 2003
    • (2003) IEEE Trans. Circuits Syst. Video Tech. , vol.13 , pp. 465-471
    • Hsia, S.-C.1
  • 6
    • 0032641123 scopus 로고    scopus 로고
    • Low-power memory mapping through reducing address bus activity
    • Sept.
    • Panda. PR., Dutt. N.D, "Low-power memory mapping through reducing address bus activity", VLSI Systems, IEEE Trans. on, vol 7, pp309-320, Sept. 1999
    • (1999) VLSI Systems, IEEE Trans. on , vol.7 , pp. 309-320
    • Panda, P.R.1    Dutt, N.D.2
  • 7
    • 84948969835 scopus 로고    scopus 로고
    • Initial memory complexity analysis of the AVC CODEC
    • K.Denolf, C.Blanch, "Initial Memory Complexity Analysis of the AVC CODEC", SIPS '02. IEEE Workshop, pp222-227
    • SIPS '02. IEEE Workshop , pp. 222-227
    • Denolf, K.1    Blanch, C.2
  • 8
    • 21644473933 scopus 로고    scopus 로고
    • http://www.samsungelectronics.com/semiconductors/


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.