Express virtual channels with capacitively driven global links

IEEE Micro

Volumn 29, Issue 4, 2009, Pages 48-61

  Krishna, Tushar ^a   Kumar, Amit ^a   Peh, Li Shiuan ^a   Postman, Jacob ^b   Chiang, Patrick ^b   Erez, Mattan ^c  

^a PRINCETON UNIVERSITY   (United States)

^b OREGON STATE UNIVERSITY   (United States)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Bandwidth; Delay; Express virtual channels; Hardware; Integrated circuit interconnections; Interconnect; Magnetic cores; Networks on chip; Presses; System on a chip; Wire

Indexed keywords

DELAY; EXPRESS VIRTUAL CHANNELS; INTEGRATED CIRCUIT INTERCONNECTIONS; INTERCONNECT; NETWORKS ON CHIP; PRESSES; SYSTEM-ON-A-CHIP;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COMMUNICATION CHANNELS (INFORMATION THEORY); ELECTRIC NETWORK TOPOLOGY; MAGNETIC CIRCUITS; MAGNETIC CORES; MAGNETIC DEVICES; MICROPROCESSOR CHIPS; OPTICAL INTERCONNECTS; PRESSES (MACHINE TOOLS); ROUTERS; WIRE;

INTEGRATED CIRCUITS;

EID: 70049084562     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2009.64     Document Type: Article

References (6)

1. A. Kumar et al., "Express Virtual Channels: Towards the Ideal Interconnection Fabric," Proc. Int'l Symp. Computer Architecture (ISCA 07), ACM Press, 2007, pp. 150-161.
2. Y. Hoskote et al., "A 5-GHz Mesh Interconnect for a Teraflops Processor," IEEE Micro, vol. 27, no. 5, Sept./Oct. 2007, pp. 51-61.
3. H.-S. Wang, L.-S. Peh, and S. Malik, "Power-Driven Design of Router Microarchitectures in On-Chip Networks," Proc. Int'l Symp. Microarchitecture (Micro 03), IEEE CS Press, 2003, pp. 105-116.
4. M.-J.E. Lee, W. Dally, and P. Chiang, "Low-Power Area-Efficient High-Speed I/O Circuit Techniques," IEEE J. Solid-State Circuits, vol. 35, no. 11, Nov. 2000, pp. 1591-1591.
5. M.M.K. Martin et al., "Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset," SIGARCH Computer Architecture News, vol. 33, no. 4, 2005, pp. 92-99.
6. N. Agarwal et al., "Garnet: A Detailed On-Chip Network Model inside a Full-System Simulator," Proc. Int'l Symp. Performance Analysis of Systems and Software (ISPASS 09), IEEE CS Press, 2009, pp. 33-42.