VLSI architecture of line-based lifting wavelet transform for motion JPEG2000

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 2, 2007, Pages 431-440

  Seo, Young Ho ^a,b   Kim, Dong Wook ^a,c  

^a Hansung University ^*

^b Hansung University   (South Korea)

^c Kwangwoon University   (South Korea)

Author keywords

ASIC; Discrete wavelet transform (DWT); Factorization; FPGA; Lifting; VLSI

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DISCRETE WAVELET TRANSFORMS; FACTORIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE COMPRESSION; PROGRAM PROCESSORS;

CMOS FABRICATION PROCESS; LIFTING PROCESSOR; WAVELET COEFFICIENTS;

VLSI CIRCUITS;

EID: 33847735946     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.889368     Document Type: Article

References (17)

1. M. Boliek, C. Christopoulos, and E. Majani, "JPEG2000 Part-I Final Draft International Standard," ISO/IEC JTC1/SC29 WG1, Aug. 24, 2000.
2. I. Daubechies and W. Sweldens, "Factoring wavelet transforms into lifting schemes," J. Fourier Anal. Appl., vol. 4, no. 3, pp. 247-269, May 1998.
3. W. Sweldens, "Lifting scheme: A new philosophy in biorthogonal wavelet constructions," in Proc. SPIE, 1995, vol. 2569, pp. 68-79.
4. K. K. Parhi and T. Nishitani, "VLSI architectures for discrete wavelet transforms," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 1, no. 2, pp. 191-202, Jun. 1993.
5. A. Grzeszczak, M. K. Mandal, S. Panchanathan, and T. Yeap, "VLSI implementation of discrete wavelet transform," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 4, no. 4, pp. 421-433, Dec. 1996.
6. G. Lafruit, L. Nachtergaele, J. Bormans, M. Engels, and I. Bolsens, "Optimal memory organization for scalable texture codecs in MPEG-4," IEEE Trans. Circuits Syst. Video Technol., vol. 9, no. 2, pp. 218-243, Mar. 1999.
7. M. Ferretti and D. Rizzo, "A parallel architecture for the 2-D discrete wavelet transform with integer lifting scheme," J. VLSI Signal Process., vol. 28, no. 3, pp. 165-185, Jul. 2001.
8. T. Acharya and C. Chakrabarti, "A survey on lifting-based discrete wavelet transform architectures," J. VLSI Signal Process. Syst., vol. 42, no. 3, pp. 321-339, Mar. 2006.
9. P.-Y. Chen, "VLSI implementation for one-dimensional multilevel lifting-based wavelet transform," IEEE Trans. Comput., vol. 53, no. 4, pp. 386-398, Apr. 2004.
10. M. Martina, G. Masera, G. Piccinini, and M. Zamboni, "Novel JPEG2000 compliant DWT and IWT VLSI implementations," J. VLSI Signal Process. Syst., vol. 35, no. 2, pp. 137-153, Sep. 2003.
11. H. Liao, M. K. Mandal, and B. F. Cockburn, "Efficient architectures for 1-D and 2-D lifting-based wavelet transforms," IEEE Trans. Signal Process., vol. 52, no. 5, pp. 1315-1326, May 2004.
12. P. Tseng, C. Huang, and L. Chen, "Reconfigurable discrete wavelet transform processor for heterogeneous reconfigurable multimedia systems," J. VLSI Signal Process. Syst., vol. 41, no. 1, pp. 35-47, Aug. 2005.
13. C. T. Huang, P. C. Tseng, and L. G. Chen, "Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform," IEEE Trans. Signal Process., vol. 52, no. 4, pp. 1080-1089, Apr. 2004.
14. K. Andra, C. Chakrabarti, and T. Acharya, "A VLSI architecture for lifting-based forward and inverse wavelet transform," IEEE Trans. Signal Process., vol. 50, no. 4, pp. 966-977, Apr. 2002.
15. G. Dillen, B. Georis, J. D. Legat, and O. Cantineau, "Combined linebased architecture for the 5-3 and 9-7 wavelet transform of JPEG2000," IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 9, pp. 944-950, Sep. 2003.
16. X. Lan, N. Zheng, and Y. Liu, "Low-power and high-speed VLSI architecture for lifting-based forward and inverse wavelet transform," IEEE Trans. Consum. Electron., vol. 51, no. 2, pp. 379-385, May 2005.
17. L. Liu, N. Chen, H. Meng, L. Zhang, Z. Wang, and H. Chen, "A VLSI architecture of JPEG2000 encoder," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2032-2040, Nov. 2004.