메뉴 건너뛰기




Volumn 55, Issue 2, 2009, Pages 322-326

A direct digital frequency synthesizer based on two segment fourth-order parabolic approximation

Author keywords

Direct digital frequency synthesizer; Parabolic approximation; Pipelining; ROM less

Indexed keywords

CLOCK RATE; CONSTANT MULTIPLIERS; DIRECT DIGITAL FREQUENCY SYNTHESIZER; FOURTH-ORDER; HARDWARE COMPLEXITY; LOWER-POWER CONSUMPTION; MAXIMUM ERROR; NOVEL DESIGN; PARABOLIC APPROXIMATION; PHASE-TO-SINUSOID AMPLITUDE CONVERSION; PIPELINING; POWER CONSUMPTION; SINGLE PHASE; SPECTRAL PURITY; SPURIOUS FREE DYNAMIC RANGE; WORST CASE;

EID: 68949181879     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2009.5174388     Document Type: Article
Times cited : (21)

References (14)
  • 1
    • 13244273508 scopus 로고    scopus 로고
    • Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis
    • Dec
    • J. M. P. Langlois and D. Al-Khalili, "Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis," IEE Proc. Circuits Devices Syst., vol.151, no.6, pp.519-528, Dec. 2004
    • (2004) IEE Proc. Circuits Devices Syst , vol.151 , Issue.6 , pp. 519-528
    • Langlois, J.M.P.1    Al-Khalili, D.2
  • 2
    • 3542990876 scopus 로고    scopus 로고
    • Direct digital frequency synthesizers with polynomial hyperfolding technique
    • Oct
    • D. De Caro, E. Napoli, and A. G. M. Strollo, "Direct digital frequency synthesizers with polynomial hyperfolding technique," IEEE Trans. Circuits and System-II Express Briefs, vol. 51, no. 7, pp. 337-334, Oct. 2004
    • (2004) IEEE Trans. Circuits and System-II Express Briefs , vol.51 , Issue.7 , pp. 337-334
    • De Caro, D.1    Napoli, E.2    Strollo, A.G.M.3
  • 4
    • 34548249069 scopus 로고    scopus 로고
    • Systematic methodology for designing low power direct digital frequency synthesizers
    • Jan
    • M. Kesoulis, D. Soudris and C. Koukourlis, "Systematic methodology for designing low power direct digital frequency synthesizers," IET Circuits Devices Syst., pp. 293-304, Jan. 2007
    • (2007) IET Circuits Devices Syst , pp. 293-304
    • Kesoulis, M.1    Soudris, D.2    Koukourlis, C.3
  • 5
    • 13244282768 scopus 로고
    • Contemporary frequency synthesis techniques
    • Gorski-PcpiclT J, Ed, IEEE Press
    • Hutchinson, B.H. Jr., "Contemporary frequency synthesis techniques," in Gorski-PcpiclT J. (Ed.): 'Frequency synthesis: techniques and applications' (IEEE Press, 1975), pp. 25-45
    • (1975) Frequency synthesis: Techniques and applications , pp. 25-45
    • Hutchinson Jr., B.H.1
  • 6
    • 0023586546 scopus 로고
    • An analysis of the output spectrum of direct digital frequency synthesizers in the presence of phase-accumulator truncation
    • Nicholas, H.T. III, and Samuel, H., "An analysis of the output spectrum of direct digital frequency synthesizers in the presence of phase-accumulator truncation," Proc. 41st Annual Symp. on Frequency Control, 1987, pp. 495-502.
    • (1987) Proc. 41st Annual Symp. on Frequency Control , pp. 495-502
    • Nicholas III, H.T.1    Samuel, H.2
  • 7
    • 0032003282 scopus 로고    scopus 로고
    • A 2V, 2GHz low-power direct digital frequency synthesizer chip-set for wireless communication
    • A. Yamagishi, M. Ishikawa, T. Tsukahara, "A 2V, 2GHz low-power direct digital frequency synthesizer chip-set for wireless communication," IEEE J. Solid-State Circuits vol. 33, no. 2, pp. 210-217, 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , Issue.2 , pp. 210-217
    • Yamagishi, A.1    Ishikawa, M.2    Tsukahara, T.3
  • 8
    • 0033878416 scopus 로고    scopus 로고
    • Low-power direct digital frequency synthesis for wireless communications
    • March
    • A. Bellaouar and S. O. Michael, "Low-power direct digital frequency synthesis for wireless communications," IEEE Journal of Solid-state Circuits, vol. 35, no. 3, pp. 385-390, March 2000
    • (2000) IEEE Journal of Solid-state Circuits , vol.35 , Issue.3 , pp. 385-390
    • Bellaouar, A.1    Michael, S.O.2
  • 9
    • 0033169555 scopus 로고    scopus 로고
    • A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range
    • Aug
    • A. Madisetti, A. Y. Kwentus, A. N. Willson, "A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range," IEEE Journal of Solid-state Circuits, vol. 34, no. 8, pp. 1034-1043, Aug. 1999
    • (1999) IEEE Journal of Solid-state Circuits , vol.34 , Issue.8 , pp. 1034-1043
    • Madisetti, A.1    Kwentus, A.Y.2    Willson, A.N.3
  • 10
    • 0035456355 scopus 로고    scopus 로고
    • A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second order parabolic approximation
    • Sep
    • A. M. Sodagar and G. R. Lahiji, "A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second order parabolic approximation," IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 48, no. 9, pp. 850-857, Sep. 2001.
    • (2001) IEEE Trans. Circuits Syst. II, Expr. Briefs , vol.48 , Issue.9 , pp. 850-857
    • Sodagar, A.M.1    Lahiji, G.R.2
  • 11
    • 0034448385 scopus 로고    scopus 로고
    • A.M. Sodagar, and Lahiji, G.R., A novel architecture for ROM-less sine-output direct digital frequency synthesizers by using the 2nd-order parabolic approximation, Proc. IEEE/IEA Int. Frequency Control Symp., Kansas City, Missouri, pp. 284-289, June 2000,
    • A.M. Sodagar, and Lahiji, G.R., "A novel architecture for ROM-less sine-output direct digital frequency synthesizers by using the 2nd-order parabolic approximation," Proc. IEEE/IEA Int. Frequency Control Symp., Kansas City, Missouri, pp. 284-289, June 2000,
  • 12
    • 33750598017 scopus 로고    scopus 로고
    • Phase-Adjustable pipelining ROM-Less direct digital frequency synthesizer with a 41.66 MHz output frequency
    • Oct
    • C. C. Wang, J. M. Huang etc., "Phase-Adjustable pipelining ROM-Less direct digital frequency synthesizer with a 41.66 MHz output frequency," IEEE Trans. Circuits and System-II Express Briefs, vol. 53, no. 10, pp. 1143-1147, Oct. 2006
    • (2006) IEEE Trans. Circuits and System-II Express Briefs , vol.53 , Issue.10 , pp. 1143-1147
    • Wang, C.C.1    Huang etc, J.M.2
  • 14
    • 0031169975 scopus 로고    scopus 로고
    • A fast parallel squarer based on divide-and-conquer
    • Jun
    • J. Yoo, K. F. Smith, and G. Gopalakrishnan, "A fast parallel squarer based on divide-and-conquer," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 909-912, Jun. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.6 , pp. 909-912
    • Yoo, J.1    Smith, K.F.2    Gopalakrishnan, G.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.