Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 10, 2006, Pages 1143-1147

  Wang, Chua Chin ^a   Huang, Jian Ming ^a   Tseng, Yih Long ^a   Lin, Wun Ji ^a   Hu, Ron ^b  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b Asuka Microelectronics Inc   (Taiwan)

Author keywords

Direct digital frequency synthesizer (DDFS); frequency synthesizer; read only memory (ROM) less; squarer decomposition; wireless network

Indexed keywords

COMMUNICATION SYSTEMS; COMPUTER ARCHITECTURE; ERROR ANALYSIS; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; PACKET NETWORKS; PIPELINE PROCESSING SYSTEMS; ROM;

DIRECT DIGITAL FREQUENCY SYNTHESIZER; SQUARER DECOMPOSITION; WIRELESS NETWORK;

FREQUENCY SYNTHESIZERS;

EID: 33750598017     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.882236     Document Type: Article

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