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Volumn , Issue , 2007, Pages 571-574

A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

EID: 68549131962     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405796     Document Type: Conference Paper
Times cited : (5)

References (11)
  • 1
    • 33646900503 scopus 로고    scopus 로고
    • Device scaling limits of si MOSFET's and their application dependencies
    • March
    • D. Frank et al. , "Device Scaling Limits of Si MOSFET's and Their Application Dependencies, " Proceedings of the IEEE, 89, March, pp. 259-288, 2001.
    • (2001) Proceedings of the IEEE , vol.89 , pp. 259-288
    • Frank, D.1
  • 3
    • 4544335291 scopus 로고    scopus 로고
    • Reverse body bias and supply collapse for low effective standby power
    • Aug
    • L. Clark, M. Morrow, and W. Brown, "Reverse Body Bias and Supply Collapse for Low Effective Standby Power, " IEEE Trans. VLSI Systems, 12, pp. 947-956, Aug. , 2004.
    • (2004) IEEE Trans. VLSI Systems , vol.12 , pp. 947-956
    • Clark, L.1    Morrow, M.2    Brown, W.3
  • 4
    • 13444270768 scopus 로고    scopus 로고
    • Low standby power state storage for sub-130-nm technologies
    • Feb
    • L. Clark, F. Ricci, and M. Biyani, "Low Standby Power State Storage for Sub-130-nm Technologies". IEEE J. Solid-state Circuits, 40, pp. 498-506, Feb. , 2005.
    • (2005) IEEE J. Solid-state Circuits , vol.40 , pp. 498-506
    • Clark, L.1    Ricci, F.2    Biyani, M.3
  • 6
    • 0033221245 scopus 로고    scopus 로고
    • An 18-?A standby current 1. 8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode
    • Nov
    • H. Mizuno, et al. , "An 18-?A standby current 1. 8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode, " IEEE J. of Solid-state Circuits, 34, pp. 1492-1500, Nov. , 1999.
    • (1999) IEEE J. of Solid-state Circuits , vol.34 , pp. 1492-1500
    • Mizuno, H.1
  • 7
    • 4544284413 scopus 로고    scopus 로고
    • Transistor optimization for leakage power management in a 65-nm CMOS technology for wireless and mobile applications
    • S. Zhao, et al. , "Transistor optimization for leakage power management in a 65-nm CMOS technology for wireless and mobile applications, " Symp. VLSI Tech. Dig. , pp. 14-15, 2004.
    • (2004) Symp. VLSI Tech. Dig , pp. 14-15
    • Zhao, S.1
  • 8
    • 84938662741 scopus 로고    scopus 로고
    • http://www. ibm. com/chips/asics/foundry/technologies/cmos. html, [online].
  • 9
    • 84938662742 scopus 로고    scopus 로고
    • http://www. eas. asu. edu/~ptm, [online].
  • 10
    • 0033712799 scopus 로고    scopus 로고
    • New paradigm of predictive MOSFET and interconnect modeling for early circuit design
    • Y. Cao, et al. , "New paradigm of predictive MOSFET and interconnect modeling for early circuit design, " Proc. IEEE Custom Integrated Circuits Conf. , pp. 201-204, 2000.
    • (2000) Proc. IEEE Custom Integrated Circuits Conf , pp. 201-204
    • Cao, Y.1
  • 11
    • 84938662743 scopus 로고    scopus 로고
    • http://www. mosis. org, [online].


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.