Optimum location of silicide/Si interface in ultra-thin body SOI MOSFETs with recessed and elevated silicide source/drain contact structure

Solid-State Electronics

Volumn 53, Issue 10, 2009, Pages 1112-1115

  Kim, Seong Dong ^a  

^a IBM RESEARCH   (United States)

Author keywords

CMOS; Elevated source drain; Series resistance; Silicon on insulator (SOI); Specific contact resistivity; Transmission line model; Ultra thin body (UTB)

Indexed keywords

CMOS; ELEVATED SOURCE/DRAIN; SERIES RESISTANCE; SILICON-ON-INSULATOR (SOI); SPECIFIC CONTACT RESISTIVITY; TRANSMISSION LINE MODEL; ULTRA-THIN BODY (UTB);

ELECTRIC LINES; ELECTROMAGNETIC WAVE EMISSION; LIGHT TRANSMISSION; MICROSENSORS; MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; TRANSMISSION LINE THEORY;

SILICIDES;

EID: 68349148332     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.06.004     Document Type: Article

References (7)

1. Su L.T., Sherony M.J., Hu H., Chung J.E., and Antoniadis D.A. Optimization of series resistance in sub-0.2 μm SOI MOSFET's. IEEE Electron Dev Lett 15 9 (1994) 363-365
2. Tsui B.Y., and Chen M.C. Series resistance of self-aligned silicided source/drain structure. IEEE Trans Electron Dev 40 1 (1993) 197-206
3. Kim SD, Narasimha S, Rim K. An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETs. In: International electron devices meeting technical digest; 2005. p. 149-52.
4. Scott D.B., Hunter W.R., and Shichijo H. A transmission line model for silicided diffusions: impact on the performance of VLSI circuits. IEEE J Solid-State Circ 17 2 (1982) 281-291
5. Reeves G.K., and Harrison H.B. An analytical model for alloyed ohmic contacts using a trilayer transmission line model. IEEE Trans Electron Dev 42 8 (1995) 1536-1547
6. Reeves G.K., and Harrison H.B. Using TLM principles to determine MOSFET contact and parasitic resistance. Solid-State Electron 41 8 (1997) 1067-1074
7. Kedzierski J, Xuan P, Anderson EH, Boker J, King TJ, Hu C. Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime. In: International electron devices meeting technical digest; 2000. p. 57-60.