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International Journal of High Speed Electronics and Systems

Volumn 19, Issue 1, 2009, Pages 23-31

A room temperature ballistic deflection transistor for high performance applications

(3) Diduck, Quentin a Irie, Hiroshi b Margala, Martin c

a School of Operations Research and Industrial Engineering (United States)

b University of Rochester (United States)

c University of Massachusetts (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BALLISTIC ELECTRON TRANSPORT; BALLISTIC TRANSPORTS; BARRIER STRUCTURES; CHANNEL SEPARATION; CIRCUIT DESIGN TECHNIQUES; DIFFERENTIAL MODE; DRAIN TERMINALS; DRAIN-SOURCE VOLTAGE; EXPERIMENTAL MEASUREMENTS; GATE BIAS; GATE WIDTHS; HETEROSTRUCTURES; HIGH MOBILITY; HIGH PERFORMANCE APPLICATIONS; INALAS; INITIAL ESTIMATE; INP SUBSTRATES; MATERIAL SYSTEMS; MEAN FREE PATH; NEGATIVE TRANSCONDUCTANCE; NOVEL DEVICES; PROTOTYPE DEVICES; ROOM TEMPERATURE; SMALL SIGNAL; STEP LITHOGRAPHY; TERMINAL DEVICES; TRANSIT TIME; TWO-DIMENSIONAL ELECTRON GAS (2DEG);

BALLISTICS; DEFLECTION (STRUCTURES); DRAIN CURRENT; ELECTRIC POTENTIAL; ELECTRON GAS; ELECTRONS; LITHOGRAPHY; TRANSCONDUCTANCE; TRANSISTORS;

TWO DIMENSIONAL ELECTRON GAS;

EID: 68349128981 PISSN: 01291564 EISSN: None Source Type: Journal
DOI: 10.1142/S0129156409006060 Document Type: Conference Paper

Times cited : (29)

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