Analysis of the dynamic avalanche of punch through insulated gate bipolar transistor (PT-IGBT)

Solid-State Electronics

Volumn 53, Issue 9, 2009, Pages 944-954

  Lefranc, P ^a   Planson, D ^b   Morel, H ^b   Bergogne, D ^b  

^a SUPELEC   (France)

^b UNIVERSITÉ DE LYON   (France)

Author keywords

Dynamic avalanche; Finite element simulation; IGBT; Mixed mode simulation

Indexed keywords

A-THERMAL; ACTIVE AREA; BUCK TOPOLOGY; FINITE ELEMENT SIMULATION; FINITE ELEMENT SIMULATORS; IGBT; INDUCTIVE LOADS; MITSUBISHI; MIXED-MODE SIMULATION; NUMERICAL SIMULATION; OVER CURRENT; PUNCH-THROUGH; SIMULATION RESULT; TEMPERATURE INCREASE;

ACTIVE FILTERS; BIPOLAR TRANSISTORS; CELL MEMBRANES; FINITE ELEMENT METHOD; INSULATED GATE BIPOLAR TRANSISTORS (IGBT); PHOTOTRANSISTORS; SOLID STATE DEVICES; THERMOANALYSIS;

SPICE;

EID: 67749103847     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.06.009     Document Type: Article

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