Low-floor decoders for LDPC codes

IEEE Transactions on Communications

Volumn 57, Issue 6, 2009, Pages 1663-1673

  Han, Yang ^a   Ryan, William E ^a  

^a University of Arizona   (United States)

Author keywords

Bi mode decoder; Bit pinning; Error floor; Generalized iterative decoder; LDPC code; Low floor decoder

Indexed keywords

BI-MODE DECODER; ERROR FLOOR; GENERALIZED ITERATIVE DECODER; LDPC CODE; LOW-FLOOR DECODER;

CODING ERRORS; FLOORS; ITERATIVE DECODING;

DECODING;

EID: 67650675057     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCOMM.2009.06.070325     Document Type: Article

References (41)

1. R. G. Gallager, Low Density Parity Check Codes. Cambridge, MA: MIT Press, 1963.
2. Y. Kou, S. Lin, and M. Fossorier, "Low-density parity-check codes based on finite geometries: A rediscovery and new results," IEEE Trans. Inform. Theory, vol. 47, pp. 2711-2736, Nov. 2001.
3. X.-Y. Hu, E. Eleftheriou, and D.-M. Arnold, "Progressive edge-growth Tanner graphs," in Proc. IEEE GlobeCom, vol. 2, pp. 995-1001, Nov. 2001.
4. T. Tian, C. Jones, J. D. Villasenor, and R. D. Wesel, "Construction of irregular LDPC codes with low error floors," in Proc. IEEE International Conf. Commun., vol. 5, pp. 3125-3129, May 2003.
5. J. Xu, L. Chen, I. Djurdjevic, S. Lin, and K. Abdel-Ghaffar, "Construction of regular and irregular LDPC codes: Geometry decomposition and masking," IEEE Trans. Inform. Theory, vol. 53, no. 1, pp. 121-134, Jan. 2007.
6. A. Abbasfar, D. Divsalar, and K. Yao, "Accumulate repeat accumulate codes," in Proc. IEEE GlobeCom, vol. 1, pp. 509-513, Nov. 2004.
7. D. Divsalar, S. Dolinar, and J. Thorpe, "Accumulate-repeat-accumulateaccumulate-codes," in Proc. 60th Veh. Technol. Conf., vol. 3, pp. 2292-2296, Sept. 2004.
8. W.-Y. Weng, A. Ramamoorthy, and R. D. Wesel, "Lowering the error floors of irregular high-rate LDPC codes by graph condition," in Proc. 60th Veh. Technol. Conf., vol. 4, pp. 2549-2553, Sept. 2004.
9. D. Divsalar and C. Jones, "Protograph based low error floor LDPC coded modulation," in Proc. IEEE Military Commun. Conf., vol. 1, pp. 378-385, Oct. 2005.
10. Y. Zhang and W. E. Ryan, "Structured IRA codes: Performance analysis and construction," IEEE Trans. Commun., to appear.
11. Y. Zhang and W. E. Ryan, "Toward low LDPC-code floors: A case study," submitted to IEEE Trans. Commun., Feb. 2007.
12. J. Lu and J. M. F. Moura, "Structured LDPC codes for high-density recording: Large girth and low error floor," IEEE Trans. Magnetics vol. 42, pp. 208-213, Feb. 2006.
13. S. K. Chilappagari, S. Sankaranarayanan, and B. Vasic, "Error floors of LDPC codes on the binary symmetric channel," IEEE International Conf. Commun., June 2006.
14. H. Xiao and A. H. Banihashemi, "Graph-based message-passing schedules for decoding LDPC codes," IEEE Trans. Commun., vol. 52, no. 12, pp. 2098-2105, Dec. 2004.
15. A. I. Vila Casado, M. Griot, and R. Wesel, "Informed dynamic scheduling for belief-propagation decoding of LDPC codes," in Proc. IEEE ICC'07 Glasgow, Scotland, June 2007.
16. E. Cavus and B. Daneshrad, "A performance improvement and error floor avoidance technique for belief propagation decoding of LDPC codes," in Proc. 16th IEEE International Symp. Personal, Indoor Mobile Radio Commun., vol. 4, pp. 2386-2390, Sept. 2005.
17. S. Lander and O. Milenkovic, "Algorithmic and combinatorial analysis of trapping sets in structured LDPC codes," in Proc. 2005 International Conf. Wireless Networks, Commun. Mobile Computing, vol. 1, pp. 630-635, June 2005.
18. M. Chertkov, "Reducing the error floor," 2007 Information Theory Workshop, Lake Tahoe, CA, Sept. 2007.
19. Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. Wainwright, "Investigation of error floors of structured low-density parity-check codes by hardware emulation," 2006 IEEE GlobeCom Conf., Nov. 2006.
20. T. Richardson, "Error floors of LDPC codes," in Proc. 41st Allerton Conf. Commun., Control, Computing, Allerton House, Monticello, IL, USA, Oct. 2003.
21. D. MacKay and M. Postol, "Weaknesses of margulis and ramanujanmargulis low-density parity-check codes," Electronic Notes Theoretical Computer Science, vol. 74, 2003.
22. G. A. Margulis, "Explicit constructions of graphs without short cycles and low-density codes," Combinatorica vol 2, no. 1, pp. 71-78, 1982.
23. J. Rosenthal and P. O. Vontobel, "Constructions of LDPC codes using Ramanujan graphs and ideas from Margulis," in Proc. 38th Annual Allerton Conf. Commun., Control, Computing, pp. 248-257, 2000.
24. B. Xia and W. E. Ryan, "On importance sampling for linear block codes," in Proc. 2003 IEEE International Conf. Commun., vol. 4, pp. 2904-2908, May 2003.
25. E. Cavus, C. Haymes, and B. Baneshrad, "A highly efficient importance sampling method for LDPC codes using trapping sets," submitted to IEEE Trans. Commun..
26. C. A. Cole, S. G. Wilson, E. K. Hall, and T. R. Giallorenzi, "A general method for finding low error rates of LDPC codes," submitted to IEEE Trans. Inform. Theory, June 2006.
27. L. Dolecek, Z. Zhang, M. Wainwright, V. Anantharam, and B. Nikoli'c, "Evaluation of the low frame error rate performance of LDPC codes using importance sampling," 2007 IEEE Inform. Theory Workshop, Sept. 2-6, 2007.
28. R. Koetter and P. Vontobel, "Graph-covers and iterative decoding of finite length codes," Turbo Conference, Brest 2003.
29. O. Milenkovic, E. Soljanin, and P. Whiting, "Asymptotic spectra of trapping sets in regular and irregular LDPC code ensembles," IEEE Trans. Inform. Theory, vol. 53, pp. 39üC55, Jan. 2007.
30. L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate," IEEE Trans. Inform. Theory, vol. 20, pp. 284-287, Mar. 1974.
31. R. McEliece, "On the BCJR trellis for linear block codes," IEEE Trans. Inf. Theory, pp. 1072-1092, July 1996.
32. R. Pyndiah, "Near optimum decoding of product codes: Block turbo codes," IEEE Trans. Commun., vol. 46, no. 8, pp. 1003-1010, Aug. 1998.
33. J. Hagenauer and P. Hoeher, "A Viterbi algorithm with soft-decision outputs and its applications," in Proc. IEEE GlobeCom, vol. 3, pp. 1680-1686, Nov. 1989.
34. C. Jones, S. Dolinar, K. Andrews, D. Divsalar, Y. Zhang, and W. Ryan, "Functions and architectures for LDPC decoding," IEEE Inform. Theory Workshop'07, Lake Tahoe, CA, Sept. 2007.
35. R. Michael Tanner, "On quasi-cyclic repeat-accumulate codes," in Proc. 37th Allerton Conf. Commun., Control, Computing, Sept. 1999.
36. J. Xu, L. Chen, L. Zeng, L. Lan, and S. Lin, "Construction of low-density parity-check codes by superposition," IEEE Trans. Commun., vol. 53, pp. 243-251, Feb. 2005.
37. T. J. Richardson and R. L. Urbanke, "Multi-edge type LDPC codes," to appear, IEEE Trans. Inform. Theory. [Online]. Available: http://lthcwww.epfl.ch/
38. J. Thorpe, "Low-Density Parity-Check (LDPC) codes constructed from protographs," JPL INP, Tech. Rep., pp. 42-154, Aug. 2003.
39. European TeleCommun. Standards Institute. "Digital video broadcasting (DVB) second generation farming structure, channel coding and modulation systems for broadcasting, interactive services, news gathering and other broadband satellite applications," DRAFT EN 302 307 DVBS2-74r15, 2003.
40. Y. Han and W. E. Ryan, "Pinning techniques for low-floor detection/ decoding of LDPC-coded partial response channels," in Proc. 2008 5th International Symposium on Turbo Codes and Related Topics, pp. 49-54,Sept. 2008.
41. F. Kschischang, B. Frey, and H.-A. Loeliger, "Factor graphs and the sum-product algorithm," IEEE Trans. Inform. Theory, pp. 498-519, Feb. 2001.