NoC interconnection functional testing: using boundary-scan to reduce the overall testing time

2009 10th Latin American Test Workshop, LATW 2009

Volumn , Issue , 2009, Pages

  Hervé, Marcos B ^a   Cota, Érika ^a   Kastensmidt, Fernanda L ^a   Lubaszewski, Marcelo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; BOUNDARY SCAN; FAULT COVERAGES; FUNCTIONAL TEST; FUNCTIONAL TESTING; IN-NETWORK; NOC TESTING; ON CHIPS; TEST CONFIGURATIONS; TEST SEQUENCE; TEST TIME; TEST TIME REDUCTION; TESTING TIME;

ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT TESTING;

TESTING;

EID: 67649861335     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LATW.2009.4813801     Document Type: Conference Paper

References (8)

1. Vermeulen, B. et. al. Bringing Communication Networks on a Chip: Test and Verification Implications, IEEE Communications Magazine, Volume 41, Issue 9, Sept. 2003, pp. 74-81.
2. Stewart, K.; Tragoudas, S.; Interconnect testing for networks on chips, VTS, 2006.
3. Grecu, C. et al. Methodologies and algorithms for testing switch-based NoC interconnects, DFT, 2005, pp. 238-246.
4. Raik, J.; Govind, V.; Ubar, R.; An External Test Approach for Network-on-a-Chip Switches, ATS, 2006, pp. 437-442.
5. Grecu, C. et al. BIST for network-on-chip interconnect infrastructures, VTS 2006.
6. Pande, P.P. et al. Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding, DFT, 2006, pp. 466-476.
7. Cota, E.; Kastensmidt, F. L.; Cassel, M., Meirelles, P., Amory, A., Lubaszewski, M., Redefining and Testing Interconnect Faults in Mesh NoCs. ITC, 2007.
8. Cota, E.; Kastensmidt, F. L.; Cassel, M., Hervé, M., Alemida, P., Meirelles, P., Amory, A., Lubaszewski, M., A High Fault Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip. IEEE Transactions on Computers (Preprint version).