A fast CMOS multiplier in nanotechnology

Journal of Applied Sciences

Volumn 8, Issue 13, 2008, Pages 2468-2473

  Assadi, Pooya ^a  

^a ISLAMIC AZAD UNIVERSITY   (Iran)

Author keywords

Carry lookahead adder; CMOS; Computer arithmetic; Redundant operands; VLSI

Indexed keywords

CARRY LOOK-AHEAD ADDER; CARRY SELECT ADDERS; COMPUTER ARITHMETIC; ELECTRONIC PARAMETERS; POWER-DELAY PRODUCTS; REDUCTION TECHNOLOGIES; REDUNDANT OPERANDS; VLSI;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRON MULTIPLIERS; FORESTRY; LOW POWER ELECTRONICS; NANOTECHNOLOGY; RESEARCH; VLSI CIRCUITS;

ADDERS;

EID: 67649534747     PISSN: 18125654     EISSN: 18125662     Source Type: Journal    
DOI: 10.3923/jas.2008.2468.2473     Document Type: Article

References (6)

1. Cho, K.J., K.C. Lee, J.G. Chung and K.K. Parhi, 2004.Design of low-error fixed-width modified booth multiplier. IEEE Trans. VLSI syst., 12: 522-531.
2. Jou, S.J., M.H. Tsai and Y.L. Tsao, 2003. Low-error reduced-width Booth multipliers for DSP applications. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 50: 1470-1474.
3. Kang, J.Y. and J.L. Gaudiot, 2006. A simple high-speed multiplier design. IEEE Trans. Comput, 55: 1253-1258.
4. Law, C.F. and S.S. Rofail, 1999. A low-power 16*16-b parallel multiplier utilizing pass-transistor logic. IEEE J. Solid State Circuits, 10: 1395-1399.
5. Sunar, B. and C.K. Koc, 2001. An efficient optimal normal basis type II multiplier. IEEE Trans. Comput., 50: 83-87.
6. Yeh, W.C. and C.W. Jen, 2000. High-speed booth encoded parallel multiplier design. IEEE Trans.Comput., 49: 692-701.