An adaptive hardware classifier in FPGA based-on a cellular compact genetic algorithm and block-based neural network

2008 International Symposium on Communications and Information Technologies, ISCIT 2008

Volumn , Issue , 2008, Pages 658-663

  Jewajinda, Yutana ^a  

^a NATIONAL ELECTRONICS AND COMPUTER TECHNOLOGY CENTER   (Thailand)

Author keywords

[No Author keywords available]

Indexed keywords

2D-ARRAYS; BLOCK-BASED NEURAL NETWORKS; COMPACT GENETIC ALGORITHM; EVOLVABLE; FPGA IMPLEMENTATIONS; HARDWARE ARCHITECTURE; HARDWARE IMPLEMENTATIONS; ONLINE EVOLUTION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NEURAL NETWORKS; PARALLEL ARCHITECTURES;

HARDWARE;

EID: 67549134766     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCIT.2008.4700275     Document Type: Conference Paper

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