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Volumn , Issue , 2008, Pages 64-70

Janus: A novel use of formal verification for targeted behavioral equivalence

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED METHODS; BEHAVIORAL EQUIVALENCE; COMPLEX DESIGNS; DESIGN CHANGE; DESIGN INTENT; FORMAL EQUIVALENCE VERIFICATION; FORMAL VERIFICATIONS; MICRO ARCHITECTURES; SIMILAR DESIGN; UNINTENDED BEHAVIOR; VALIDATION METHODS; VERIFICATION FRAMEWORK;

EID: 67449147364     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2008.4695876     Document Type: Conference Paper
Times cited : (1)

References (12)
  • 1
    • 0000318151 scopus 로고
    • A theory and implementation of sequential hardware equivalence
    • Carl Pixley. A theory and implementation of sequential hardware equivalence. IEEE Trans. on CAD of Integrated Circuits and Systems, 11(12):1469-1478, 1992.
    • (1992) IEEE Trans. on CAD of Integrated Circuits and Systems , vol.11 , Issue.12 , pp. 1469-1478
    • Pixley, C.1
  • 6
    • 21244493661 scopus 로고    scopus 로고
    • Principles of sequential-equivalence verification
    • DOI 10.1109/MDT.2005.68
    • Maher N. Mneimneh and Karem A. Sakallah. Principles of sequential-equivalence verification. IEEE Des. Test, 22(3):248-257, 2005. (Pubitemid 40889825)
    • (2005) IEEE Design and Test of Computers , vol.22 , Issue.3 , pp. 248-257
    • Mneimneh, M.N.1    Sakallah, K.A.2
  • 12
    • 19944370138 scopus 로고    scopus 로고
    • Reference model based rtl verification: An integrated approach
    • Nov.
    • N. Hung, W.N.N.; Narasimhan. Reference model based rtl verification: an integrated approach. In High- Level Design Validation and Test Workshop, 2004. Ninth IEEE International, pages 9-13, Nov. 2004.
    • (2004) High- Level Design Validation and Test Workshop , vol.2004 , pp. 9-13
    • Hung, N.1    Narasimhan, W.N.N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.