Hardware implementation of skeletonization algorithm for parallel asynchronous image processing

Journal of Signal Processing Systems

Volumn 56, Issue 1, 2009, Pages 91-103

  Lopich, Alexey ^a   Dudek, Piotr ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

Asynchronous processing; Binary skeletonization; Grassfire transformation; Wave propagations

Indexed keywords

APPLICATION SPECIFICS; ASYNCHRONOUS PROCESSING; ASYNCHRONOUS PROCESSORS; BINARY SKELETONIZATION; CELLULAR PROCESSOR ARRAYS; GRASSFIRE TRANSFORMATION; HARDWARE IMPLEMENTATIONS; INHOMOGENEITY; PROOF-OF-CONCEPT DESIGNS; SKELETONIZATION ALGORITHMS; WAVE PROPAGATION VELOCITIES;

CRACK PROPAGATION; HARDWARE; IMAGE PROCESSING; WAVE PROPAGATION;

PARALLEL ALGORITHMS;

EID: 67349210619     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-008-0283-6     Document Type: Article

References (50)

1. Z. Ju Jia Y. Hong 2001 Skeletonization of ribbon-like shapes based on regularity and singularity analyses IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics) 31 3 401 407
2. L. Lam S. W. Lee C. Y. Suen 1992 Thinning methodologies-A comprehensive survey IEEE Transactions on Pattern Analysis and Machine Intelligence 14 9 869 885
3. Y. Xia 1989 Skeletonization via the realization of the fire front's propagation and extinction in digital binary shapes IEEE Transactions on Pattern Analysis and Machine Intelligence 11 10 1076 1086 (Pubitemid 20628922)
4. C. Arcelli G. Sanniti di Baja 1993 Euclidean skeleton via centre-of-maximal-disc extraction Image and Vision Computing 11 3 163 173
5. Chehadeh, Y., Coquin, D., & Bolon, P. (1996). A skeletonization algorithm using chamfer distance transformation adapted to rectangular grids pp. 131-135. Vienna: IEEE Comput. Soc. Press.
6. Vincent, L. (1991). Exact Euclidean distance function by chain propagations pp. 520-525. Maui: IEEE Comput. Soc. Press.
7. Wai-Pak, C., Kin-Man, L., & Wan-Chi, S. (2000). An efficient and accurate algorithm for extracting a skeleton pp. 742-745. Barcelona: IEEE Comput. Soc.
8. Andrews, D., Kancler, C., & Wealand, B. (1996). An embedded real-time SIMD processor array for image processing pp. 131-134. Honolulu: IEEE Comput. Soc. Press.
9. J.-E. Eklund C. Svensson A. Astrom 1996 VLSI implementation of a focal plane image processor - a realization of the near-sensor image processing concept IEEE Transaction on VLSI Systems 4 3 322 335 (Pubitemid 126785650)
10. Kleihorst, R. P., Abbo, A. A., van der Avoird, A., Op de Beeck, M. J. R., Sevat, L., Wielage, P., et al. (2001). Xetal: a low-power high-performance smart camera processor. in ISCAS2001 pp. 215-218. Sydney: IEEE.
11. S. Kyo T. Koga S. Okazaki I. Kuroda 2003 A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements IEEE Journal of Solid-State Circuits 38 11 1992 2000
12. G. C. Linan A. Rodriguez-Vazquez R. C. Galan F. Jimenez-Garrido S. Espejo R. Dominguez-Castro 2004 A 1000 FPS at 128∈×∈128 vision processor with 8-bit digitized I/O IEEE Journal of Solid-State Circuits, 2003 European Solid State Circuits Conference (ESSCIRC) 39 7 1044 1055
13. L. Lindgren J. Melander R. Johansson B. Moller 2005 A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging IEEE Journal of Solid-State Circuits 40 6 1350 1359
14. P. Dudek P. J. Hicks 2005 A general-purpose processor-per-pixel analogue SIMD vision chip IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 52 1 13 20
15. T. Komuro S. Kagami M. Ishikawa 2004 A dynamically reconfigurable SIMD processor for a vision chip IEEE Journal of Solid-State Circuits 39 1 265 268
16. P. Dudek 2006 An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 53 5 354 358 (Pubitemid 43786577)
17. T. Roska L. O. Chua 1993 CNN universal machine. An analogic array computer IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 40 3 163 173 (Pubitemid 23700453)
18. Lopich, A., & Dudek, P. (2005). Architecture of asynchronous cellular processor array for image skeletonization. in ECCTD05 pp. 81-84. Cork: IEEE.
19. A. Rosenfeld J. L. Pfaltz 1968 Distance functions on digital pictures Pattern Recognition 1 33 61
20. Borgefors, G., & Sanniti di Baja, G. (1988). Skeletonizing the distance transform on the hexagonal grid pp. 504-507. Rome: IEEE Comput. Soc. Press.
21. Shih, F. Y., & Pu, C. C. (1990). Medial axis transformation with single-pixel and connectivity preservation using Euclidean distance computation pp. 723-725. Piscataway: IEEE.
22. Do Hyun, C., & Sapiro, G. (2000). Segmentation-free skeletonization of gray-scale images via PDEs pp. 927-930. Vancouver: IEEE.
23. Verwer, B. J. H. (1988). Improved metrics in image processing applied to the Hilditch skeleton pp. 137-142. Rome: IEEE Comput. Soc. Press.
24. Z. Kalmar Z. Marczell C. Szepesvari A. Lorincz 1999 Parallel and robust skeletonization built on self-organizing elements Neural Networks 12 1 163 173 (Pubitemid 29118354)
25. C. Rekeczky L. O. Chua 1999 Computing with front propagation: Active contour and skeleton models in continuous-time CNN Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 23 2-3 373 402 (Pubitemid 30526164)
26. Serra, J. (1982). Image analysis and mathematical morphology. London: Academic.
27. S. Beucher 1994 Digital skeletons in Euclidean and geodesic spaces Signal Processing 38 1 127 141
28. N. Bourbakis N. Steffensen B. Saha 1997 Design of an array processor for parallel skeletonization of images IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 44 4 284 298 (Pubitemid 127768249)
29. N. Sudha 2003 Design of a cellular architecture for fast computation of the skeleton Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 35 1 61 73
30. P. Tzionas P. Tsalides A. Thanailakis 1995 A parallel skeletonization algorithm based on two-dimensional cellular automata and its VLSI implementation Real-Time Imaging 1 2 105 117
31. N. G. Bourbakis 1989 A parallel-symmetric thinning algorithm Pattern Recognition 22 4 387 396
32. A. Favre H. Keller 1983 Parallel syntactic thinning by recording of binary pictures Computer Vision, Graphics, and Image Processing 23 1 99 112 (Pubitemid 13573673)
33. C. M. Holt A. Stewart M. Clint R. H. Perrott 1987 An improved parallel thinning algorithm Communications of the ACM 30 2 156 160 (Pubitemid 17532983)
34. S. Suzuki K. Abe 1987 Binary picture thinning by an iterative parallel two-subcycle operation Pattern Recognition 20 3 297 307 (Pubitemid 17617066)
35. A. Bel-Lan L. Montoto 1981 A thinning transform for digital images Signal Processing 3 1 37 47 (Pubitemid 11479878)
36. A. Rosenfeld L. S. Davis 1976 A note on thinning IEEE Transactions on Systems, Man and Cybernetics SMC-6 3 226 228
37. R. Stefanelli A. Rosenfeld 1971 Some parallel thinning algorithms for digital pictures Journal of the Association for Computing Machinery 18 2 255 264
38. C. Yung-Sheng H. Wen-Hsing 1988 A modified fast parallel algorithm for thinning digital patterns Pattern Recognition Letters 7 2 99 106
39. T. Y. Zhang C. Y. Suen 1984 A fast parallel algorithm for thinning digital patterns Communications of the ACM 27 3 236 239 (Pubitemid 14581473)
40. C. J. Hilditch 1969 Linear skeletons from square cupboards Machine Intelligence 4 403 420
41. S. Hauck 1995 Asynchronous design methodologies: An overview Proceedings of the IEEE 83 1 69 93
42. I. David R. Ginosar M. Yoeli 1992 An efficient implementation of Boolean functions as self-timed circuits IEEE Transactions on Computers 41 1 2 11
43. Furber, S. B., Day, P., Garside, J. D., Paver, N. C., & Woods, J. V. (1994). A micropipelined ARM [microprocessor] (pp. 211-220). Grenoble, France.
44. Jacobs, G. M., & Brodersen, R. W. (1988). Self-timed integrated circuits for digital signal processing applications pp. 197-208. Monterey: IEEE Press.
45. N. R. Poole 1994 Self-timed logic circuits Electronics & Communication Engineering Journal 6 6 261 270
46. Peeters, A., & van Berkel, K. (1995). Single-rail handshake circuits. In Proceedings Second Working Conference on Asynchronous Design Methodologies, 30-31 May 1995 pp. 53-62. London: IEEE Comput. Soc. Press.
47. Dean, M. E., Dill, D. L., & Horowitz, M. (1991). Self-timed logic using current-sensing completion detection (CSCD). In IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3), 14-16 Oct. 1991 pp. 187-191. Cambridge: IEEE Comput. Soc. Press.
48. Nehaniv, C. L. (2002). Self-reproduction in asynchronous cellular automata. in NASA/DoD Conference (pp. 201-209).
49. P. Dudek S. Szczepanski J. V. Hatfield 2000 A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line IEEE Journal of Solid-State Circuits 35 2 240 247 (Pubitemid 30557812)
50. Ranganathan, N., & Doreswamy, K. B. (1995). A VLSI chip for computing the medial axis transform of an image. In Proceedings of Conference on Computer Architectures for Machine Perception, 18-20 September pp. 36-43. Como: IEEE Comput. Soc. Press.