A low-power and bandwidth-efficient motion estimation IP core design using binary search

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 19, Issue 5, 2009, Pages 760-765

  Wang, Shih Hao ^a   Tai, Shih Hsin ^a   Chiang, Tihao ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Bandwidth efficient; Low power; Motion estimation (ME); MPEG 4

Indexed keywords

ARCHITECTURE DESIGNS; B-FRAME; BANDWIDTH EFFICIENT; BI-DIRECTIONAL SEARCH; BINARY MOTION ESTIMATIONS; BINARY SEARCH; BLOCK SEARCHES; BUS BANDWIDTH; EFFICIENT ALGORITHM; EFFICIENT MOTION ESTIMATION; IP CORE; ITS ARCHITECTURE; KEY ISSUES; LOW POWER; MACROBLOCK-LEVEL; MATCHING CRITERION; MPEG-4; PARALLEL PROCESSING; PORTABLE VIDEO; POWER CONSUMPTION; PRE-PROCESSING; SEARCH STRUCTURES;

ARCHITECTURAL DESIGN; BANDWIDTH; BLOCK CODES; BUSES; COMPOSITE MICROMECHANICS; ESTIMATION; MOTION PICTURE EXPERTS GROUP STANDARDS;

MOTION ESTIMATION;

EID: 67249096535     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2009.2017416     Document Type: Article

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