A multi-core sphere decoder VLSI architecture for MIMO communications

GLOBECOM - IEEE Global Telecommunications Conference

Volumn , Issue , 2008, Pages 3297-3302

  Yang, Chia Hsiang ^a   Marković, Dejan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BER PERFORMANCE; DATA RATES; DEPTH FIRST SEARCH; ENERGY EFFICIENCY IMPROVEMENTS; MAXIMUM-LIKELIHOOD DETECTION; MIMO COMMUNICATION; MULTI CORE; MULTI-INPUT MULTI-OUTPUT; MULTICORE ARCHITECTURES; PROCESSING ELEMENTS; PROPOSED ARCHITECTURES; SEARCH SPEED; SPHERE DECODERS; SPHERE DECODING ALGORITHM; VLSI ARCHITECTURES;

COMPUTATIONAL COMPLEXITY; ENERGY EFFICIENCY; MAXIMUM LIKELIHOOD; MULTIPLEXING; SPHERES;

DECODING;

EID: 67249092866     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/GLOCOM.2008.ECP.633     Document Type: Conference Paper

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