A VLSI 8 × 8 MIMO near-ML decoder engine

2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS

Volumn , Issue , 2006, Pages 387-392

  Knagge, Geoff ^a   Bickerstaff, Mark ^b   Ninness, Brett ^a   Weller, Steven R ^a   Woodward, Graeme ^b  

^a UNIVERSITY OF NEWCASTLE   (Australia)

^b Agere Systems   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; ENERGY CONSERVATION; MIM DEVICES; SIGNAL PROCESSING; TELECOMMUNICATION; TELECOMMUNICATION SYSTEMS; VLSI CIRCUITS;

EXPONENTIAL COMPLEXITY; HIGH SPEEDS; MAXIMUM LIKELIHOOD (ML) DECODER; MAXIMUM LIKELIHOOD (MLET); MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) DETECTION; MULTIPLE-INPUT-MULTIPLE-OUTPUT (MIMO) SYSTEMS; POWER SAVINGS; SIGNAL PROCESSING SYSTEMS; WIRELESS (WIFI) COMMUNICATION;

MULTIPLEXING;

EID: 46249100219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2006.352614     Document Type: Conference Paper

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