Real-time application to multiprocessor-system-on-chip mapping strategy for system-level design tool

Electronics Letters

Volumn 45, Issue 12, 2009, Pages 613-615

  Jia, Z J ^a   Bautista, T ^a   Nunez A ^a  

^a UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED MULTIPROCESSORS; INTER PROCESSOR COMMUNICATION; MAPPING STRATEGY; MULTIPROCESSOR-SYSTEM; PHASE MAPPINGS; PROCESSOR LOADS; REAL-TIME APPLICATION; RESOURCE USAGE; STATIC MAPPING; SYSTEM LEVEL DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

MULTIPROCESSING SYSTEMS;

EID: 67149116623     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el.2009.0952     Document Type: Article

References (6)

1. Erbas, C.: System-level modeling and design space exploration for multiprocessor embedded system-on-chip architecture , 2006, PhD, University of Amsterdam, The Netherlands
2. Jia, Z.J., Bautista, T., Núñez, A., Guerra, C., and Hernández, M.: Design space exploration and performance analysis for modular design of CVS in a heterogeneous MPSoC , Proc. 2008 Int. Conf. on Reconfigurable Computing and FPGAs, December, 2008, p. 193-198
3. Reyes, V., Kruijtzer, W., Bautista, T., Ghiath, A., and Núñez, A.: A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study , Proc. Conf. on Design, Automation and Test in Europe, 2006, p. 474-479
4. El-Rewini, H., Ali, H.H., and Lewis, T.: Task scheduling in multiprocessing system , IEEE Computer, 1995, 28, (12), p. 27-37
5. Lothar, T., Iuliana, B., Wolfgang, H., and Kai, H.: Mapping applications to tiled multiprocessor embedded systems , Proc. 7th Int. Conf. on Application of Concurrency to System Design, July, 2007, p. 29-40
6. Guangyu, C., Feihui, L., Son, S.W., and Kandemir, M.: Application mapping for chip multiprocessors , Proc. 45th ACM/IEEE Design Automation Conf., June, 2008, p. 620-625