Overcoming DRAM scaling limitations by employing straight recessed channel array transistors with 〈100〉 uni-axial and {100} uni-plane channels

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 319-322

  Kim, I G ^a   Park, S H ^a   Yoon, J S ^a   Kim, D J ^a   Noh, J Y ^a   Lee, J H ^a   Kim, Y S ^a   Hwang, M W ^a   Yang, K H ^a   Park, Joosung ^a   Oh, Kyungseok ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DATA REDUCTION; TRANSISTORS; WORD PROCESSING;

RECESSED CHANNEL ARRAY TRANSISTORS (RCAT);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 33847729869     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Chul Lee, et al., "Enhaced Data Retention of Damascene-fmFET DRAM with Local Channel Implantation and 〈100〉 Fin Surface Orientation Engineering," IEDM Tech.Dig. 2004
2. H. Sayama, et al.,"Effect of 〈100〉 Channel Direction for High Performance SCE Immune pMOSFET with Less than 0.15um Gate Length," IEDM Tech.Dig.1999,p658.
3. Leland Chang, et al., "CMOS Circuit Performance Enhancement by Surface Orientation Optimization," IEEE TED VOL 51, NO. 10 2004.
4. Kwyro Lee,et.al., "Physical Understanding of Low-Field Carrier Mobility in Silicon MOSFET Inversion Layer," IEEE TED VOL 38, NO.8 August 1991.