Process development for ultra low loop reverse wire bonding on copper bond pad metallization

Proceedings of 4th Electronics Packaging Technology Conference, EPTC 2002

Volumn , Issue , 2002, Pages 356-360

  Ganesh, V P ^a   Sivakumar, M ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

AUGER ELECTRON SPECTROSCOPY; CHIP SCALE PACKAGES; COPPER; ELECTRON SPECTROSCOPY; ELECTRONICS PACKAGING; GOLD; GOLD METALLOGRAPHY; INTEGRATED CIRCUIT INTERCONNECTS; METALLIZING; METALS; NICKEL; WAFER BONDING; WIRE;

AUGER ELECTRON SPECTROSCOPIES (AES); BOND PAD METALLIZATION; ELECTROLESS NICKEL IMMERSION GOLD; ELECTROLESS NICKEL IMMERSION GOLD PLATINGS; HIGH-DENSITY PACKAGING; LOW COST PRODUCTS; PARAMETER OPTIMIZATION; PROCESS DEVELOPMENT;

WIRE PRODUCTS;

EID: 84964626561     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2002.1185697     Document Type: Conference Paper

References (4)

1. International Technology Roadmap for Semiconductor 2001 (ITRS 2001)
2. Lee Smith and Ted Tessier, "Stacked Chip Scale Packages: They are Not Just for Cell Phones Anymore!", Chip Scale Review, July 2001, Pages 53-61
3. Mark Klossner and Steve Babinetz, "Assembly Solutions for 3-D Stacked Devices", Semicon Singapore 2002, Singapore pp 37-46
4. Paul Reid, Ivy Wei Qin, Ph.D., Paul Bereznycky, and Jeff Swiatek, "Providing Stacked Die Solution with Wedge Bonding Technology", Semicon Singapore 2002, Singapore pp 47-55