A comparison between V-ramp TDDB techniques for reliability evaluation

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2008, Pages 133-136

  Aal, A ^a  

^a ELMOS Semiconductor AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTANT VOLTAGE STRESS TESTS; HIGH-Κ; MEASUREMENT DATA; RAMP TESTING; RELIABILITY EVALUATION; RELIABILITY MEASUREMENTS; TEST DATA; THICK OXIDES; TIME CONSTRAINTS; VOLTAGE TESTS;

RELIABILITY;

EID: 64549095201     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2008.4796104     Document Type: Conference Paper

References (7)

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2. A. Aal, "Fast prediction of gate oxide reliability", IEEE Proc. Integrated Reliability Workshop, Final Report, 2006, pp. 182-185.
3. A. Berman, 'Time-Zero Dielectric Reliability Test By A Ramp Method", IEEE Proc. Int. Rel. Phys. Symp., 1981, pp. 204-209
4. O. Aubel et al., "New Approach of 90 nm Low- κ Interconnect Evaluation using a Voltage Ramp Dielectric Breakdown Test", IEEE Proc. Int. Rel. Phys. Symp., 2005, pp. 483-489
5. A. Aal, "Fast Wafer Level Reliability Assessment Of Ultra Thick Oxides Under Impact Ionization Conditions", IEEE Proc. Integrated Reliability Workshop, Final Report, 2007, pp. 117-120
6. S. C. Fan et al., "Accurate Characterization On Intrinsic Gate Oxide Reliability Using Voltage Ramp Tests", IEEE Proc. Int. Rel. Phys. Symp., 2006, pp. 625-626
7. G. S. Haase et al., "Breakdown Characteristics Of Interconnect Dielectrics", IEEE Proc. Int. Rel. Phys. Symp., 2005, pp. 466-473