New approach of 90NM low-k interconnect evaluation using a voltage ramp dielectric breakdown (VRDB) test

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2005, Pages 483-489

  Aubel, Oliver ^a   Kiene, Michael ^a   Yao, Walter ^b  

^a AMD Saxony ^*  (Germany)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCONNECT EVALUATION; PRODUCT LIFETIME; SAMPLE SIZE; TEMPERATURE DEPENDENCE;

DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; ELECTRIC POTENTIAL; FAILURE ANALYSIS; INTEGRATED CIRCUITS; SAMPLING; STRESS ANALYSIS;

INTERCONNECTION NETWORKS;

EID: 28744454314     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. T.D. Sullivan, "Reliability considerations for copper metallization for ULSI circuits, Conf. Proc. American Institute of Physics 1999, No.491, pp. 39-50, 1999
2. W. Wu, S.H. Kang, et.al., Thermal effect on electromigration performance for Al/SiO2, Cu/SiO2 and Cu/low-k interconnect systems, Solid State Electron, Vol.45, pp.59-62, 2001
3. K.Y. Yiang T.S. Mok, et.al., "Reliability improvements using buried capping layer in advanced interconnects", pp.333-337, IRPS 2004
4. S.M. Sze, "Physics of Semiconductor Devices", John Wiley & Sins, New York, 1981
5. G.B. Alers, K. Jow, et.al., "Interlevel Dielectric Failures in Copper / Low-k structures", IEEE T Dev Mat Reliab, Vol.4, No.2, pp. 148-152, June 2004
6. F. Chen, IRPS 2005, to be published