Performance evaluation and ASIC design of LDPC decoder for IEEE 802.11n

2009 6th IEEE Consumer Communications and Networking Conference, CCNC 2009

Volumn , Issue , 2009, Pages

  Syafei, W A ^c   Yohena, R ^a   Shimajiri, H ^b   Yoshida, T ^a   Kurosaki, M ^c   Nagao, Y ^c   Sai, B ^c   Ochi, H ^c,d  

^a UNIVERSITY OF THE RYUKYUS   (Japan)

^b Frontier Okinawa 21 Co Ltd   (Japan)

^c KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^d Radrix Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; CONVOLUTIONAL CODES; DECODING; ELECTRIC BATTERIES; STANDARDS;

ASIC DESIGNS; CMOS TECHNOLOGIES; CODING RATES; IEEE 802.11N; LDPC CODES; LDPC DECODERS; LOGIC SYNTHESIS; LOW-DENSITY PARITY-CHECK CODES; LOW-POWER; PERFORMANCE ENHANCEMENTS; PERFORMANCE EVALUATIONS; SIMULATION RESULTS;

INTEGRATED CIRCUITS;

EID: 63749102408     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCNC.2009.4784735     Document Type: Conference Paper

References (12)

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