Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 503-510

  Shimizu, Kazunori ^a   Ishikawa, Tatsuyuki ^a   Togawa, Nozomu ^a   Ikenaga, Takeshi ^a   Goto, Satoshi ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTER HARDWARE; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; ITERATIVE METHODS; PIPELINE PROCESSING SYSTEMS;

BIT NODE; CHECK NODES; MESSAGE PASSING ALGORITHM; PIPELINE ARCHITECTURE;

DECODING;

EID: 33748561451     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.83     Document Type: Conference Paper

References (11)

1. D. J. C. Mackay, "Good error-correctiong codes based on very sparse matrices," IEEE Trans. on Information Theory, Vol.47, pp.498-519, 2001.
2. S.Y. Chung, G.D. Forney Jr., T.J. Richardson, R.L. Urbanke, "On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit," IEEE Communications letters, Vol.5, No.2, Feb. 2001.
3. T.J. Richardson and R.L. Urbanke, "The capacity of low-density parity-check codes under message-passing decoding", IEEE Trans. on. Information Theory, vol.42, no.2, pp.599-618, 2001.
4. R. G. Gallager, Low-Density Parity-Check Codes, MIP Press, Cambridge, MA, 1963.
5. A. Blanksby and C. Howland, "A 690-mW 1-Gbps 1024-b, rate-1/2 Low-Density Parity-Check Code Decoder," IEEE Journal of Solid State Circuits, Vol.37, pp.404-412, Mar., 2002.
6. E. Liao, E. Yeo and B. Nikolic, "Low-density parity-check code constructions for hardware implementation," Proceedings 2004 IEEE International Conference on Communications, ICC'04, Paris, pp.2573-2577, June, 2004.
7. Y. Chen and D. Hocevar, "A FPGA and ASIC Implementation of Rate 1/2 8088-b Irregular Low Density Parity Check Decoder," IEEE Global Telecmmunications Conference, GLOBECOM'03, pp. 113-117, 2003.
8. M. Mansour and N. Shanbhag, "Low Power VLSI Decoder Architectures for LDPC Codes," Proc. of the. International Sympo, on Low Power Electronics and Design, pp.284-289, 2002.
9. Marjan Karkooti and Joseph R. Cavallaro, "Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding," IEEE Proceedings of International Conference on Information Technology: Coding and Computing, ITCC'04, pp.579-585, Vol 1, Apr., 2004.
10. M. Fossorier, M. Mihaljevic and H. Imai, "Reduced Complexity Iterative Decoding of Low Density Parity Check Codes Based on Belief Propagation", IEEE Transactions on Communications, vol. 47, pp. 673-680, May 1999.
11. Xilinx, Inc., Vertex-II Platform FPGAs: Complete Data Sheet, DS031 (v3.3), pp.21-22, June, 2004.