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Volumn , Issue , 2007, Pages 507-510

Power-efficient decision-feedback equalizers for multi-Gb/s CMOS serial links (invited)

Author keywords

CMOS; Decision feedback equalizers; High speed I O; Low power; Receivers; Serial links

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DECISION MAKING; ENERGY DISSIPATION; SIGNAL DISTORTION;

EID: 34748876506     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2007.380934     Document Type: Conference Paper
Times cited : (10)

References (9)
  • 1
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    • T. Beukema et al., "A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2633-2645, Dec. 2005.
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  • 2
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  • 4
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    • Dec
    • J. F. Bulzaeehelli et al., "A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology," IEEE I. Solid-State Circuits, vol. 41, no. 12, pp. 2885-2900, Dec. 2006.
    • (2006) IEEE I. Solid-State Circuits , vol.41 , Issue.12 , pp. 2885-2900
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  • 5
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  • 6
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    • A 5-mW 6-Gb/s quarter-rate, sampling receiver with a 2-tap DFE using soft decisions
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    • K.-L. Wong, A. Rylyakov, and C.-K. Yang, "A 5-mW 6-Gb/s quarter-rate, sampling receiver with a 2-tap DFE using soft decisions," IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 190-191, June 2006.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.