Simultaneous-sweep method for evaluation of single-electron transistors with barriers induced by gate electric field

Japanese Journal of Applied Physics, Part 2: Letters

Volumn 43, Issue 8 B, 2004, Pages

  Inokawa, Hiroshi ^a   Takahashi, Yasuo ^b  

^a Kashino Diverse Brain Research Laboratory of NTT Communication Science Laboratories   (Japan)

^b HOKKAIDO UNIVERSITY   (Japan)

Author keywords

Gate induced barrier; Metal oxide semiconductor field effect transistor (MOSFET); Simultaneous sweep method; Single electron transistor (SET)

Indexed keywords

CAPACITANCE; ELECTRIC POTENTIAL; ELECTRON TRANSITIONS; FABRICATION; MOSFET DEVICES; OPTIMIZATION; POLYSILICON; SEMICONDUCTOR QUANTUM DOTS; SEMICONDUCTOR QUANTUM WIRES; TRANSCONDUCTANCE;

GATE VOLTAGE; GATE-INDUCED BARRIERS; SIMULTANEOUS-SWEEP METHOD; SINGLE-ELECTRON TRANSISTOR (SET);

ELECTRON DEVICES;

EID: 6344253097     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.43.L1048     Document Type: Article

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9. o = |s|, expressions in the main text are derived.
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