Non-intrusive dynamic application profiler for detailed loop execution characterization

Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08

Volumn , Issue , 2008, Pages 23-30

  Nair, Ajay ^a   Lysecky, Roman ^a  

^a University of Arizona   (United States)

Author keywords

Dynamic optimization; Embedded systems; Nonintrusive; Profiling

Indexed keywords

ACCURATE PERFORMANCE; AREA OVERHEADS; DESIGN PROCESS; DYNAMIC APPLICATIONS; DYNAMIC OPTIMIZATION; HARDWARE SYSTEMS; NONINTRUSIVE; PROFILING;

APPLICATIONS; INTEGRATED CIRCUITS; PROGRAM COMPILERS;

EMBEDDED SYSTEMS;

EID: 63349104718     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1450095.1450102     Document Type: Conference Paper

References (29)

1. Anderson, J., et al. Continuous Profiling: Where Have All the Cycles Gone? 16th ACM Symp. of Operating Systems Design, 1997.
2. Bala, V., E. Duesterwald, S. Banerjia. Dynamo: A Ttransparent Runtime Optimization System, Conf. on Programming Language Design and Implementation, 2000.
3. Bellas, N., et al. Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. ICCD, 1999.
4. Calder, B., P. Feller, A. Eustace. Value Profiling. MICRO, 1997.
5. Chung, E.Y., L. Benini and G. De Micheli. Automatic Source Code Specialization for Energy Reduction. ISLPED, 2001.
6. Chernoff, A. Herdeg, M. Hookway, R. Reeve, C. Rubin, N. Tye, T. Bharadwaj Yadavalli, S. Yates, J. FX!32 A Profile-Directed Binary Translator, IEEE Micro, Vol 18, No. 2, pp. 56-64, 1998.
7. Conte, T. M., Patel, B. A., Menezes, K. N., and Cox, J. S. 1996. Hardware-based profiling: an effective technique for profile-driven optimization. International Journal of Parallel Programming, Vol. 24, No. 2, pp. 187-206, 1996.
8. Dean, J., et al. ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors. MICRO, 1997.
9. Diaconescu, A., A. Mos, J. Murphy. Automatic Performance Management in Component Based Software Systems, International Conference on Autonomic Computing, May 2004.
10. Ebcioglu, K., E. Altman, M. Gschwind, S. Sathaye. Dynamic Binary Translation and Optimization. Transactions on Computers, Vol 50, June 2001.
11. Gordon-Ross, A., S. Cotterell, F. Vahid. Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example. IEEE Computer Architecture Letters, January 2002.
12. Gordon-Ross, A., F. Vahid. Frequent Loop Detection using efficient Non-Intrusive On-Chip Hardware. IEEE Transaction on Computers, Vol 54, October 2005.
13. Graham, S.L., P.B. Kessler, M.K. McKusick. gprof: a Call Graph Execution Profiler. Symposium on Compiler Construction, 1982.
14. Guo, Z., Buyukkurt, B., Najjar, W., Vissers, K. Optimized Generation of Data-Path from C Codes. Design Automation and Test in Europe Conference (DATE), pp. 112-117, 2005.
15. Guthaus, M., J. Ringenberg, D. Ernst, T. Austin, T. Mudge, R. Brown. MiBench: A Free, Commercially Representative Embedded Benchmark Suite. Workshop on Workload Characterization, 2001.
16. Hazelwood, K., A. Klauser. A Dynamic Binary Instrumentation Engine for the ARM Architecture. Conf. on Compiler, Architecture and Synthesis for Embedded Systems (CASES), 2006.
17. Keane, J., C. Bradley, C. Ebeling. A Compiled Accelerator for Biological Cell Signaling Simulations. International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 233-241, 2004.
18. Klaiber, A. The Technology Behind Crusoe Processors. Transmeta Corporation, http://www.transmeta.com, 2000.
19. Lakshminarayana, G., et al. Common-Case Computation: A High-Level Technique for Power and Performance Optimization. Design Automation Conference (DAC), 1999.
20. Larus, R. James, Schmarr Eric. EEL: Machine Independent Executable Editing. Conference on Programming Language Design and Implementation, 1995.
21. Lee, L. H., Moy er, B., Arends, J. Instruction Fetch Energy Reduction Using Loop Caches for Embedded Applications with Small Tight Loops. Intl. Symp. on Low Power Electronics and Design, 1999.
22. Lysecky, R., G. Stitt, F. Vahid. Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 3, pp. 659-681, 2006.
23. Merten, M. C., Trick, A. R., George, C. N., Gyllenhaal, J. C., and Hwu, W. W. 1999. A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization. SIGARCH Computer Architecture News, Vol. 27, No. pp. 136-147, 1999.
24. Sprunt, B. Pentium 4 Performance Monitoring Features. IEEE Micro, Vol. 22, July 2002.
25. Venkataramani, G., W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm. A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture. Conf. on Compiler, Architecture and Synthesis for Embedded Systems, 2001.
26. Villarreal, J., R. Lysecky, S. Cotterell, F. Vahid. Loop Analysis of Embedded Applications. UCR Techn. Report UCR-CSE-01-03, 2001.
27. Yellin, D. M. Competitive Algorithms for the Dynamic Selection of Component Implementations, IBM Systems Journal, Autonomic Computing, Vol. 42, 2003.
28. Zagha, M., B. Larson, S. Turner, M. Itzkowitz. Performance Analysis Using the MIPS R10000 Performance Counters. Supercomputing, Nov. 1996.
29. Zhang, X., et al. System Support for Automatic Profiling and Optimization. Intl. Symp. on Operating Systems Principles, 1997.